%0 Journal Article
%T Two-dimensional threshold voltage analytical model of DMG strained-silicon-on-insulator MOSFETs<br>异质栅全耗尽型应变硅 SOI MOSFET二维解析模型*
%A Li Jin
%A Liu Hongxi
%A Li Bin
%A Cao Lei
%A Yuan Bo
%A <br>李劲
%A 刘红侠
%A 李斌
%A 曹磊
%A 袁博
%J 半导体学报
%D 2010
%I 
%X For the first time, a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator (DMG SSOI) MOSFETs is developed. We investigate the improved short channel effect (SCE), hot carrier effect (HCE), drain-induced barrier-lowering (DIBL) and carrier transport efficiency for the novel structure MOSFET. The analytical model takes into account the effects of different metal gate lengths, work functions, the drain bias and Ge mole fraction in the relaxed SiGe buffer. The surface potential in the channel region exhibits a step potential, which can suppress SCE, HCE and DIBL. Also, strained-Si and SOI structure can improve the carrier transport efficiency, with strained-Si being particularly effective. Further, the threshold voltage model correctly predicts a "rollup" in threshold voltage with decreasing channel length ratios or Ge mole fraction in the relaxed SiGe buffer. The validity of the two-dimensional analytical model is verified using numerical simulations. oindent
%K SOI MOSFETs
%K strained-Si
%K dual-material gate
%K short channel effect
%K hot carrier effect
%K the drain-induced barrier-lowering
%K two-dimensional model oindent<br>SOI
%K MOSFETs，应变硅，异质栅，短沟道效应，漏致势垒降低，二维模型
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=025C8057C4D37C4BA0041DC7DE7C758F&aid=7E8069E0A344F94B26CB27BE56D18578&yid=140ECF96957D60B2&vid=4AD960B5AD2D111A&iid=5D311CA918CA9A03&sid=F3E62E89B07D246F&eid=B31275AF3241DB2D&journal_id=1674-4926&journal_name=半导体学报&referenced_num=0&reference_num=0