%0 Journal Article
%T EOS Failure Analysis and Die Attach Optimization<br>芯片的EOS失效分析及焊接工艺优化
%A Wu Dinghe
%A Shen Meng
%A Shao Xuefeng
%A Yu Hongkun
%A <br>吴顶和
%A 沈萌
%A 邵雪峰
%A 俞宏坤
%J 半导体学报
%D 2008
%I 
%X To investigate the influence of electrical overstress (EOS) on the reliability of power MOSFETs, failure analysis is employed to assess the reliability of devices, including defects related to solder void, gate openings, and die cracks.After using finite element analysis, a circuit simulation, and a reliability accelerated test, the root cause of EOS is confirmed.EOS resistance of the devices after optimizing the die attach temperature-time curve is compared with that of the devices before the optimization using unclamped inductive loading test.The volume of solder void is observably decreased and EOS resistance is improved after optimization.
%K EOS
%K failure analysis
%K MOSFET
%K die attach
%K process optimization<br>电过应力
%K 失效分析
%K MOSFET
%K 芯片焊接
%K 工艺优化
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=025C8057C4D37C4BA0041DC7DE7C758F&aid=67EF61CFB9516DFD31F93A8125FB8C8B&yid=67289AFF6305E306&vid=771469D9D58C34FF&iid=0B39A22176CE99FB&sid=B9B90065CF5CD7F0&eid=B54EB62E9D3FF31E&journal_id=1674-4926&journal_name=半导体学报&referenced_num=0&reference_num=12