%0 Journal Article
%T A Fast Acquisition PLL with Wide Tuning Range<br>一种快捕获宽调节范围的锁相环
%A Ge Yan
%A Jia Song
%A Ye Hongfei
%A Ji Lijiu
%A <br>葛岩
%A 贾嵩
%A 叶红飞
%A 吉利久
%J 半导体学报
%D 2007
%I 
%X 提出了一种快捕获,低抖动,宽调节范围的增益自适应锁相环的设计.在这个方案中,采用了双边触发的鉴频鉴相器(dual-edge-triggered phase frequency detector)和自调节压控振荡器(self-regulated voltage controlled oscillator)并进行了详细的分析.芯片的加工工艺是0.5μm 1P3M CMOS标准数字逻辑工艺.测试结果表明输入频率变化在捕获范围的37%时,捕获时间为150ns;输出频率为640MHz时,均方根抖动为39ps.
%K PLL
%K fast acquisition
%K low jitter
%K wide tuning range<br>锁相环
%K 快捕获
%K 低抖动
%K 宽调节范围
%K PLL
%K fast
%K acquisition
%K low
%K jitter
%K wide
%K tuning
%K range
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=025C8057C4D37C4BA0041DC7DE7C758F&aid=AB676BA8DD97032B&yid=A732AF04DDA03BB3&vid=D3E34374A0D77D7F&iid=38B194292C032A66&sid=683005D16807E4FE&eid=23410D0BDB501DF5&journal_id=1674-4926&journal_name=半导体学报&referenced_num=4&reference_num=13