%0 Journal Article
%T Design of pn Mixed Pull-Down Network Domino XOR Gate in 45nm Technology<br>45nm工艺pn混合下拉网络多米诺异或门设计
%A Wang Jinhui
%A Gong N
%A Geng Shuqin
%A Hou Ligang
%A Wu Wuchen
%A Dong Limin
%A <br>汪金辉
%A 宫娜
%A 耿淑琴
%A 侯立刚
%A 吴武臣
%A 董利民
%J 半导体学报
%D 2008
%I 
%X A pn mixed pull-down network technique is proposed, based on the application of pMOS transistor and nMOS transistor in the pull-down network,to lower the power and improve the performance of the domino circuits.First,a domino XOR gate with this technique is designed.Compared to the standard N type domino XOR gate,its static power and dynamic power are reduced by up to 46% and 3%,respectively.Second,using this technique,the dual-threshold voltage techniques and the multiple supply voltages techniques,a novel domino XOR gate is present and its static power and dynamic power are reduced by up to 82% and 21%,as compared to the standard N type domino XOR gate.At last,the minimum static power state of four XOR gates and AC noise margins are analyzed and obtained thoroughly.
%K XOR gate
%K pn mixed pull-down network
%K dynamic power
%K static power<br>异或门
%K pn混合网络
%K 动态功耗
%K 静态功耗
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=025C8057C4D37C4BA0041DC7DE7C758F&aid=16C35C72FD78044D5A506CC7E7B81A36&yid=67289AFF6305E306&vid=771469D9D58C34FF&iid=59906B3B2830C2C5&sid=162CE18E988A6D2B&eid=91EAE2015CCB136A&journal_id=1674-4926&journal_name=半导体学报&referenced_num=0&reference_num=16