%0 Journal Article
%T Simulation and Experiment on a Buried-Oxide Trench-Gate Bipolar-Mode JFET<br>埋氧沟槽栅双极模式JFET的仿真与实验
%A Tian Bo
%A Wu Yu
%A Hu Dongqing
%A Han Feng
%A Kang Baowei
%A <br>田波
%A 吴郁
%A 胡冬青
%A 韩峰
%A 亢宝位
%J 半导体学报
%D 2008
%I 
%X A buried-oxide trench-gate bipolar-mode JFET (BTB-JFET) with an oxide layer buried under the gate region to reduce the gate-drain capacitance Cgd is proposed.Simulations with a resistive load circuit for power loss comparison at high frequency application are performed with 20V-rated power switching devices,including a BTB-JFET,a trench MOSFET (T-MOSFET) generally applied in present industry,and a conventional trench-gate bipolar-mode JFET (TB-JFET) without buried oxide,for the first time.The simulation results indicate that the switching power loss of the normally-on BTB-JFET is improved by 37% and 14% at 1MHz compared to the T-MOSFET and the normally-on TB-JFET,respectively.In order to demonstrate the validity of the simulation,the normally-on TB-JFET and BTB-JFET have been fabricated successfully for the first time,where the buried oxide structure is realized by thermal oxidation.The experimental results show that the Cgd of the BTB-JFET is decreased by 45% from that of the TB-JFET at zero source-drain bias.Compared to the TB-JFET,the switching time and switching power loss of the BTB-JFET decrease approximately by 7.4% and 11% at 1MHz,respectively.Therefore,the normally-on BTB-JFET could be pointing to a new direction for the R&D of low voltage and high frequency switching devices.
%K TB-JFET
%K BTB-JFET
%K buried oxide
%K gate-drain capacitance
%K switching power loss<br>沟槽栅双极模式JFET
%K 埋氧沟槽栅双极模式JFET
%K 埋氧
%K 栅漏电容
%K 开关功率损耗
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=025C8057C4D37C4BA0041DC7DE7C758F&aid=237D7AF80B5921151D3FD8D0658CAB7A&yid=67289AFF6305E306&vid=771469D9D58C34FF&iid=F3090AE9B60B7ED1&sid=C7BC59D607A1E67B&eid=F488521195FD61A9&journal_id=1674-4926&journal_name=半导体学报&referenced_num=1&reference_num=7