%0 Journal Article
%T Transient Characteristic Analysis of a Double-Gate Dual-Strained-Channel SOI CMOS<br>双栅双应变沟道全耗尽SOI CMOS的瞬态特性分析
%A Sun Liwei
%A Gao Yong
%A Yang Yuan
%A Liu Jing
%A <br>孙立伟
%A 高 勇
%A 杨媛
%A 刘静
%J 半导体学报
%D 2008
%I 
%X Transient characteristic analysis of a CMOS circuit based on a double-gate dual-strained channel SOI MOSFET with the effective gate length scaling down to 25nm is presented.As a result of simulations,by the adoption of a single-gate (SG) control mechanism,the conversion time from logic 1 to logic 0 is shorter for conventional strained-Si CMOS than unstrained CMOS.Furthermore,the conversion time from logic 0 to logic 1 can be reduced by the application of a strained-SiGe CMOS circuit.However,the CMOS circuit based on the novel structure can reduce tHL and tLH simultaneously.By the adoption of a double-gate (DG) control mechanism,the conversion time of the CMOS circuit shows a dramatic reduction compared with the SG control mechanism and the performance of the CMOS circuit can be improved significantly.
%K CMOS<br>双栅
%K 双应变沟道
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=025C8057C4D37C4BA0041DC7DE7C758F&aid=D8976AA86267E64DC907F3BABCC12E96&yid=67289AFF6305E306&vid=771469D9D58C34FF&iid=5D311CA918CA9A03&sid=330226EF26D09028&eid=EC8C1F9A3D77BCB9&journal_id=1674-4926&journal_name=半导体学报&referenced_num=0&reference_num=11