%0 Journal Article
%T Influence of back-gate stress on the back-gate threshold voltage of a LOCOS-isolated SOI MOSFET<br>背栅应力对LOCOS隔离的SOI器件背栅阈值电压的影响
%A Mei Bo
%A Bi Jinshun
%A Li Duoli
%A Liu Sinan
%A Han Zhengsheng
%A <br>梅博
%A 毕津顺
%A 李多力
%A 刘思南
%A 韩郑生
%J 半导体学报
%D 2012
%I 
%X The performance of a LOCOS-isolated SOI MOSFET heavily depends on its back-gate characteristic, which can be affected by back-gate stress. A large voltage stress was applied to the back gate of SOI devices for at least 30 s at room temperature, which could effectively modify the back-gate threshold voltage of these devices. This modification is stable and time invariant. In order to improve the back-gate threshold voltage, positive substrate bias was applied to NMOS devices and negative substrate bias was applied to PMOS devices. These results suggest that there is a leakage path between source and drain along the silicon island edge, and the application of large back-gate bias with the source, drain and gate grounded can strongly affect this leakage path. So we draw the conclusion that the back-gate threshold voltage, which is directly related to the leakage current, can be influenced by back-gate stress.
%K back-gate
%K threshold voltage
%K stress
%K silicon-on-insulator<br>背栅，阈值电压，应力，绝缘体上硅
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=025C8057C4D37C4BA0041DC7DE7C758F&aid=4CFB0EE1AD3DD1DF885DB1E38F76AAEA&yid=99E9153A83D4CB11&vid=27746BCEEE58E9DC&iid=0B39A22176CE99FB&sid=30AEC656943C03C6&eid=94C357A881DFC066&journal_id=1674-4926&journal_name=半导体学报&referenced_num=0&reference_num=11