%0 Journal Article
%T A new shallow trench and planar gate MOSFET structure based on VDMOS technology<br>一种基于VDMOS技术的浅沟槽平面栅MOSFET新结构
%A Wang Cailin
%A Sun Cheng
%A <br>王彩琳
%A 孙丞
%J 半导体学报
%D 2011
%I 
%X This paper proposes a new shallow trench and planar gate MOSFET (TPMOS) structure based on VDMOS technology, in which the shallow trench is located at the center of the n- drift region between the cells under a planar polysilicon gate. Compared with the conventional VDMOS, the proposed TPMOS device not only improves obviously the trade-off relation between on-resistance and breakdown voltage, and reduces the dependence of on-resistance and breakdown voltage on gate length, but also the manufacture process is compatible with that of the VDMOS without a shallow trench, thus the proposed TPMOS can offer more freedom in device design and fabrication.
%K power MOSFET
%K shallow trench
%K planar gate<br>功率MOSFET
%K 浅沟槽
%K 平面栅
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=025C8057C4D37C4BA0041DC7DE7C758F&aid=786307CB160BCFD25DB84B3A7A51B6FD&yid=9377ED8094509821&vid=9971A5E270697F23&iid=0B39A22176CE99FB&sid=CE1EE88D091BF25B&eid=E158A972A605785F&journal_id=1674-4926&journal_name=半导体学报&referenced_num=0&reference_num=0