%0 Journal Article
%T A binary-weighted 64-dB programmable gain amplifier with a DCOC and AB-class buffer<br>64dB二进制增益控制带有DCOC和AB类buffer的可编程增益放大器
%A Ye Xiangyang
%A Wang Yunfeng
%A Zhang Haiying
%A Wang Qingpu
%A <br>叶向阳
%A 王云峰
%A 张海英
%A 王卿璞
%J 半导体学报
%D 2012
%I 
%X This paper designs a binary-weighted programmable gain amplifier (PGA) with a DC offset cancellation (DCOC) circuit and an AB-class output buffer. The PGA adopts the circuit topology of a differential amplifier with diode-connected loads. Simulation shows that the performance of the PGA is not sensitive to temperature and process variation. According to test results, controlled by a digital signal of six bits, the PGA can realize a dynamic gain of -2 to 61 dB, and a gain step of 1 dB with a step error within ± 0.38 dB. The minimum 3 dB bandwidth is 92 MHz. At low-gain mode, IIP3 is 17 dBm, and a 1 dB compression point can reach 5.7 dBm. The DCOC circuit enables the amplifier to be used in a direct-conversion receiver and the AB-class output buffer circuit reduces the overall static power consumption.
%K PGA
%K DCOC
%K AB class buffer
%K binary-weighted<br>可编程增益放大器
%K dBm
%K AB类
%K 二进制
%K 加权
%K 缓冲区
%K 电路拓扑结构
%K 数字信号控制
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=025C8057C4D37C4BA0041DC7DE7C758F&aid=4CFB0EE1AD3DD1DF3E3AC861E1633046&yid=99E9153A83D4CB11&vid=27746BCEEE58E9DC&iid=0B39A22176CE99FB&sid=6D185E3C724B5256&eid=B31275AF3241DB2D&journal_id=1674-4926&journal_name=半导体学报&referenced_num=0&reference_num=11