%0 Journal Article
%T Graph theory for FPGA minimum configurations<br>FPGA芯片最少配置的图论方法研究
%A Ruan Aiwu
%A Li Wenchang
%A Xiang Chuanyin
%A Song Jiangmin
%A Kang Shi
%A Liao Yongbo
%A <br>阮爱武
%A 李文昌
%A 项传银
%A 宋江民
%A 康实
%A 廖永波
%J 半导体学报
%D 2011
%I 
%X A traditional bottom-up modeling method for minimum configuration numbers is adopted for the study of FPGA minimum configurations. This method is limited if a large number of LUTs and multiplexers are presented. Since graph theory has been extensively applied to circuit analysis and test, this paper focuses on the modeling FPGA configurations. In our study, an internal logic block and interconnections of an FPGA are considered as a vertex and an edge connecting two vertices in the graph, respectively. A top-down modeling method is proposed in the paper to achieve minimum configuration numbers for CLB and IOB. Based on the proposed modeling approach and exhaustive analysis, the minimum configuration numbers for CLB and IOB are five and three, respectively.
%K graph theory
%K minimum configuration number
%K FPGA
%K CLB
%K IOB<br>FPGA
%K 配置
%K 图论
%K 建模方法
%K CLB
%K 复用器
%K LUT
%K IFA
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=025C8057C4D37C4BA0041DC7DE7C758F&aid=A0C0AC355ED3D77497BCD131903FB622&yid=9377ED8094509821&vid=9971A5E270697F23&iid=708DD6B15D2464E8&sid=D0380CDD5865E160&eid=94C357A881DFC066&journal_id=1674-4926&journal_name=半导体学报&referenced_num=0&reference_num=9