%0 Journal Article
%T A high performance 90 nm CMOS SAR ADC with hybrid architecture<br>基于混合结构的一种高性能90nm CMOS逐次逼近A/D转换器
%A Tong Xingyuan
%A Chen Jianming
%A Zhu Zhangming
%A Yang Yintang
%A <br>佟星元
%A 陈剑鸣
%A 朱樟明
%A 杨银堂
%J 半导体学报
%D 2010
%I 
%X A 10-bit 2.5 MS/s SAR A/D converter is presented.In the circuit design,an R-C hybrid architecture D/A converter,pseudo-differential comparison architecture and low power voltage level shifters are utilized.Design challenges and considerations are also discussed.In the layout design,each unit resistor is sided by dummies for good matching performance,and the capacitors are routed with a common-central symmetry method to reduce the nonlinearity error.This proposed converter is implemented based on 90 nm CMOS ...
%K analog-to-digital converter
%K CMOS integrated circuits
%K level shifters
%K multi-supply SoC
%K high performance<br>模/数转换
%K CMOS模拟电路
%K 电平转换器
%K 多电源SoC
%K 高性能
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=025C8057C4D37C4BA0041DC7DE7C758F&aid=B91CBF5BAE5F84DD7B300088A38079B4&yid=140ECF96957D60B2&vid=4AD960B5AD2D111A&iid=CA4FD0336C81A37A&sid=B4A56061AF526896&eid=DF92D298D3FF1E6E&journal_id=1674-4926&journal_name=半导体学报&referenced_num=0&reference_num=14