%0 Journal Article
%T Design of 700 V triple RESURF nLDMOS with low on-resistance<br>Design of 700V Triple RESURF LDMOS with Low On-resistance
%A Yin Shan
%A Qiao Ming
%A Zhang Yongman
%A Zhang Bo
%A <br>银杉
%A 乔明
%A 张永满
%A 张波
%J 半导体学报
%D 2011
%I 
%X A 700 V triple RESURF nLDMOS with a low specific on-resistance of 100 mΩ·cm2 is designed. Compared with a conventional double RESURF nLDMOS whose P-type layer is located on the surface of the drift region, the P-type layer of a triple RESURF nLDMOS is located within it. The difference between the locations of the P-type layer means that a triple RESURF nLDMOS has about a 30% lower specific on-resistance at the same given breakdown voltage of 700 V. Detailed research of the influences of various parameters on breakdown voltage, specific on-resistance, as well as process tolerance is involved. The results may provide guiding principles for the design of triple RESURF nLDMOS.
%K nLDMOS
%K triple RESURF
%K breakdown voltage
%K specific on-resistance
%K charge sharing<br>
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=025C8057C4D37C4BA0041DC7DE7C758F&aid=A0C0AC355ED3D774999B26A710381D11&yid=9377ED8094509821&vid=9971A5E270697F23&iid=708DD6B15D2464E8&sid=BB4005F94361E3EE&eid=E158A972A605785F&journal_id=1674-4926&journal_name=半导体学报&referenced_num=0&reference_num=16