%0 Journal Article
%T A 2.5 mW 370 mV/pF high linearity stray-immune symmetrical readout circuit for capacitive sensors<br>2.5 mW 370mV/pF 高线性度不受寄生电容影响的全对称电容式传感器读出电路
%A Zhou Kaimin
%A Wang Ziqiang
%A Zhang Chun
%A Wang Zhihua
%A <br>周凯敏
%A 王自强
%A 张春
%A 王志华
%J 半导体学报
%D 2012
%I 
%X A stray-insensitive symmetrical capacitance-to-voltage converter for capacitive sensors is presented. By introducing a reference branch, a symmetrical readout circuit is realized. The linear input range is increased, and the systematic offsets of two input op-amps are cancelled. The common-mode noise and even-order distortion are also rejected. A chopper stabilization technique is adopted to further reduce the offset and flicker noise of the op-amps, and a Verilog-A-based varactor is used to model the real variable sensing capacitor. Simulation results show that the output voltage of this proposed readout circuit responds correctly, while the under-test capacitance changes with a frequency of 1 kHz. A metal-insulator-metal capacitor array is designed on chip for measurement, and the measurement results show that this circuit achieves sensitivity of 370 mV/pF, linearity error below 1% and power consumption as low as 2.5 mW. This symmetrical readout circuit can respond to an FPGA controlled sensing capacitor array changed every 1 ms.
%K capacitance-to-voltage converter
%K chopper stabilization
%K high linearity
%K low power<br>电容式传感器
%K 读出电路
%K 高线性
%K 对称
%K PF
%K Verilog-A
%K 运算放大器
%K 免疫
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=025C8057C4D37C4BA0041DC7DE7C758F&aid=649CF1A01F52D57193B067B8A7CFCD04&yid=99E9153A83D4CB11&vid=27746BCEEE58E9DC&iid=B31275AF3241DB2D&sid=52ED053E9A589DE5&eid=94C357A881DFC066&journal_id=1674-4926&journal_name=半导体学报&referenced_num=0&reference_num=12