%0 Journal Article
%T A process simplification scheme for fabricating CMOS polycrystalline-Si thin film transistors<br>一種製作互補式金氧半複晶矽薄膜電晶體之製程簡化技術
%A Juang Miin-Horng
%A Chang Chia-Wei
%A Shye Der-Chih
%A Hwang Chuan-Chou
%A Wang Jih-Liang
%A Jang Sheng-Liang
%A <br>庄敏宏
%A 张家伟
%A 史德智
%A 黄全洲
%A 王志良
%A 张胜良
%J 半导体学报
%D 2010
%I 
%X A process simplification scheme for fabricating CMOS poly-Si thin-film transistors (TFTs) has been proposed, which employs large-angle-tilt-implantation of dopant through a gate sidewall spacer (LATITS). By this LATITS scheme, a lightly doped drain region under the oxide spacer is formed by low-dose tilt implantation of phosphorus (or boron) dopant through the spacer, and then the nC-source/drain (nC-S/D) (or pC-S/D) region is formed via using the same photo-mask layer during CMOS integration. For both n-TFT and p-TFT devices, as compared to the sample with conventional single nC-S/D (or pC-S/D) structure, the LATITS scheme can cause an obviously smaller leakage current, due to more gradual dopant distribution and thus smaller electric field. In addition, the resultant on-state currents only show slight degradation for the LATITS scheme. As a result, by the LATITS scheme, CMOS poly-Si TFT devices with an on/off current ratio well above 8 orders may be achieved without needing extra photo-mask layers during CMOS integration.
%K polycrystalline-Si thin-film transistor
%K process simplification
%K large-angle-tilt-implantation<br>複晶矽薄膜電晶體
%K 製程簡化
%K 大角度離子佈值
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=025C8057C4D37C4BA0041DC7DE7C758F&aid=52806A707E66058B6F0179B31F413B00&yid=140ECF96957D60B2&vid=4AD960B5AD2D111A&iid=B31275AF3241DB2D&sid=67F2070E7C6DECBA&eid=94C357A881DFC066&journal_id=1674-4926&journal_name=半导体学报&referenced_num=0&reference_num=0