%0 Journal Article
%T Theoretical Analysis of Effect of LUT Size on Area and Delay of FPGA
%A Gao Haixia
%A Yang Yintang
%A Dong Gang
%A <br>Gao
%A Haixi
%A Yang
%A Yintang
%A an
%A Dong
%A Gang
%J 半导体学报
%D 2005
%I 
%X Based on architecture analysis of island-style F PGA,area and delay models of LUT FPGA are proposed.The models are used to analyze the effect of LUT size on FPGA area and performance.Results show optimal LUT size obtained by computation models is the same as that from experiments:a LUT size of 4 produces the best area results,and a LUT size of 5 provides the better performance.
%K FPGA
%K LUT
%K computation models
%K area
%K delay<br>FPGA
%K LUT
%K computation
%K models
%K area
%K delay
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=025C8057C4D37C4BA0041DC7DE7C758F&aid=CDE76193CDDE7308&yid=2DD7160C83D0ACED&vid=96C778EE049EE47D&iid=94C357A881DFC066&sid=3DC9CEF02B8360EE&eid=9124D83E61CF1CD0&journal_id=1674-4926&journal_name=半导体学报&referenced_num=1&reference_num=13