%0 Journal Article
%T Optimal Stack Generation for CMOS Analog Modules with Parasitic and Mismatch Constraints<br>带寄生及匹配约束的CMOS模拟电路模块的STACK生成优化方法(英文)
%A Zeng Xuan
%A LI Ming-yuan
%A ZHAO Wen-qing
%A TANG Pu-shan
%A ZHOU Dian
%A <br>曾璇
%A 李明原
%A 赵文庆
%A 唐璞山
%A 周电
%J 半导体学报
%D 2001
%I 
%X The performances of analog circuits depend greatly on the layout parasitics and mismatches.Novel techniques are proposed for modeling the distributed parasitic capacitance,parasitic parameter mismatch due to process gradient and the inner stack routing mismatch.Based on the proposed models,an optimal stack generation technique is developed to control the parasitics and mismatches,optimize the stack shape and ensure the generation of an Eulerian graph for a given CMOS analog module.An OPA circuit example is given to demonstrate that the circuit performances such as unit gain bandwidth and phase margin are enhanced by the proposed layout optimization method.
%K analog constraints
%K analog circuits layout
%K stack generation<br>模拟约束
%K 模拟电路版图设计
%K STACK生成
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=025C8057C4D37C4BA0041DC7DE7C758F&aid=619448AFE4C12DBF&yid=14E7EF987E4155E6&vid=BC12EA701C895178&iid=CA4FD0336C81A37A&sid=CA4FD0336C81A37A&eid=F3090AE9B60B7ED1&journal_id=1674-4926&journal_name=半导体学报&referenced_num=3&reference_num=13