%0 Journal Article
%T Non-Rectilinear On-Chip Interconnect--An Efficient Routing Solution with High Performance<br>非直角互连——布线技术发展的新趋势
%A Hong Xianlong
%A Zhu Qi
%A Jing Tong
%A Wang Yin
%A Yang Yang
%A Cai Yici
%A <br>洪先龙
%A 朱祺
%A 经彤
%A 王垠
%A 杨旸
%A 蔡懿慈
%J 半导体学报
%D 2003
%I 
%X With advance in fabrication technology of integrated circuit (IC),the increment of transistors inside one chip has been following the Moore's Law.We can design a chip with more and more functions,which enables system-on-a-chip (SOC) integration.Meanwhile,we face challenges of SOC.One of them is the interconnect effects,which may cause longer delay and heavier crosstalk.To solve the problem,many interconnect performance optimization algorithms have been proposed.However,when the algorithms are designed based on rectilinear on-chip interconnect architecture,the optimization capability is limited.So,researchers begin to present other on-chip interconnect architectures to obtain better optimization result and higher performance.Non-rectilinear on-chip interconnect architectures become a field of active research.Some studies have been made since 1990's.But,those studies are very scattered and incomplete.In this paper,we intend to survey and analyze them.We concentrate on the fundamental problems and key technologies in non-rectilinear on-chip interconnect architectures.We also discuss the corresponding researches and solutions in this research field.
%K IC
%K CAD
%K 布线
%K Steiner树
%K λ几何结构
%K 非直角互连
%K 系统级芯片
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=025C8057C4D37C4BA0041DC7DE7C758F&aid=526ABF53C3AD0FFB&yid=D43C4A19B2EE3C0A&vid=B91E8C6D6FE990DB&iid=38B194292C032A66&sid=4966445AEEBA9556&eid=FD7C952458BFB5D8&journal_id=1674-4926&journal_name=半导体学报&referenced_num=4&reference_num=56