%0 Journal Article
%T Delay of Logic Gate Driving Large RLC Interconnect Tree<br>驱动复杂RLC互连树的逻辑门延时
%A Dong Gang
%A Yang Yintang
%A Li Yuejin
%A <br>董刚
%A 杨银堂
%A 李跃进
%J 半导体学报
%D 2004
%I 
%X 提出了一个用于估计RL C互连树驱动点导纳的闭端等效π模型,并将其用于驱动复杂RL C互连树的逻辑门延时的估计中.与其他方法相比,它具有结构简单、精度较高的特点
%K delay of logic gate
%K RLC interconnect tree
%K driving point admittance<br>逻辑门延时
%K RLC互连树
%K 驱动点导纳
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=025C8057C4D37C4BA0041DC7DE7C758F&aid=D89080273D88D87C&yid=D0E58B75BFD8E51C&vid=C5154311167311FE&iid=5D311CA918CA9A03&sid=E1D875FA50925809&eid=FC27EB98080C89E6&journal_id=1674-4926&journal_name=半导体学报&referenced_num=3&reference_num=7