%0 Journal Article
%T An Effectual IC''''s Yield Estimation Model<br>一种有效的IC成品率估算模型
%A Zhao Tianxu
%A Hao Yue
%A Ma Peijun
%A <br>赵天绪
%A 郝跃
%A 马佩军
%J 半导体学报
%D 2002
%I 
%X The new computational model of the chip fault probability and IC's yield is given based on the mechanism of a chip with a defect that causes fault.The yield parameters are extracted by a realizable system of IC functional yield simulator,XD YES,for a practical circuit XT 1 and those parameters are used to compute yield of XT 1 by this new model.The result computed is in agreement with the result tested.
%K functional yield
%K defects
%K fault rate<br>功能成品率
%K 缺陷
%K 故障率
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=025C8057C4D37C4BA0041DC7DE7C758F&aid=45431666B9242B30&yid=C3ACC247184A22C1&vid=EA389574707BDED3&iid=0B39A22176CE99FB&sid=FEF02B4635FE8227&eid=974CBB04624305A1&journal_id=1674-4926&journal_name=半导体学报&referenced_num=4&reference_num=6