%0 Journal Article
%T A Systematical Approach for Noise in CMOS LNA
%A FENG Dong
%A Shi Bingxue
%A <br>Feng
%A Dong
%A an
%A Shi
%A Bingxue
%J 半导体学报
%D 2005
%I 
%X A systematic approach is used to analyze the noise in CMOS low noise amplifier(LNA),including channel noise and induced gate noise in MOS devices.A new analytical formula for noise figure is proposed.Based on this formula,the impacts of distributed gate resistance and intrinsic channel resistance on noise performance are discussed.Two kinds of noise optimization approaches are performed and applied to the design of a 5.2GHz CMOS LNA.
%K amplifier noise
%K channel noise
%K channel resistance
%K induced gate noise
%K low noise amplifier
%K noise optimization<br>放大器噪声
%K 沟道噪声
%K 沟道电阻
%K 感应栅噪声
%K 低噪声放大器
%K 噪声优化
%K amplifier
%K noise
%K channel
%K noise
%K channe
%K resistance
%K induced
%K gate
%K noise
%K low
%K noise
%K amplifier
%K noise
%K optimization
%K CMOS
%K low
%K noise
%K amplifier
%K 低噪声放大器
%K 系统研究方法
%K Noise
%K Approach
%K noise
%K optimization
%K design
%K impacts
%K distributed
%K induced
%K gate
%K noise
%K intrinsic
%K channel
%K noise
%K resistance
%K performance
%K Based
%K analytical
%K formula
%K noise
%K figure
%K MOS
%K devices
%K systematic
%K approach
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=025C8057C4D37C4BA0041DC7DE7C758F&aid=EFA5F67F9B0C8E52&yid=2DD7160C83D0ACED&vid=96C778EE049EE47D&iid=38B194292C032A66&sid=036D726259190A01&eid=8C267C8DC97FEEEF&journal_id=1674-4926&journal_name=半导体学报&referenced_num=1&reference_num=14