%0 Journal Article
%T Synthesis Scheme for Low Power Designs Under Timing Constraints
%A Wang Ling
%A Wen Dongxin
%A Yang Xiaozong
%A Jiang Yingtao
%A <br>Wang Ling
%A Wen Dongxin
%A Yang Xiaozong
%A and Jiang Yingta
%J 半导体学报
%D 2005
%I 
%X To minimize the power consumption with resources operating at multiple voltages a time-constrained algorithm is presented.The input to the scheme is an unscheduled data flow graph (DFG),and timing or resource constraints.Partitioning is considered with scheduling in the proposed algorithm as multiple voltage design can lead to an increase in interconnection complexity at layout level.That is,in the proposed algorithm power consumption is first reduced by the scheduling step,and then the partitioning step takes over to decrease the interconnection complexity.The time-constrained algorithm has time complexity of O(n 2),where n is the number of nodes in the DFG.Experiments with a number of DSP benchmarks show that the proposed algorithm achieves the power reduction under timing constraints by an average of 46 5%.
%K low power
%K multiple supply voltages
%K partitioning
%K timing constraints
%K scheduling<br>低功耗
%K 多供应电压
%K 分区
%K 时间限制
%K 调度
%K low
%K power
%K multiple
%K supply
%K voltages
%K partitioning
%K timing
%K constraints
%K scheduling
%K 基于时间
%K 限制条件
%K 低功耗
%K 高层综合
%K 设计方案
%K Timing
%K Constraints
%K Low
%K Power
%K Scheme
%K Experiments
%K benchmarks
%K show
%K power
%K reduction
%K timing
%K constraints
%K average
%K number
%K nodes
%K time
%K complexity
%K decrease
%K step
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=025C8057C4D37C4BA0041DC7DE7C758F&aid=147111B37C13CEB1&yid=2DD7160C83D0ACED&vid=96C778EE049EE47D&iid=0B39A22176CE99FB&sid=EBD6B792C9111B87&eid=2AC7DCCBBC26ECF8&journal_id=1674-4926&journal_name=半导体学报&referenced_num=4&reference_num=12