%0 Journal Article
%T Switch-Level Timing Simulation Using RC Network as Delay Model<br>用RC网络作延迟模型的开关级定时模拟
%A Hu Yi/Sichuan Institute of Solid-State Circuits
%A Sichuan
%A YongchuanWang Zhaoming/Chengdu Institute of Radio Engineering
%A Chengdu
%A <br>胡易
%A 王兆明
%J 半导体学报
%D 1989
%I 
%X A new method for switch-level timing simulation is proposed.We suggest that the timingsimulation should be performed by two steps.First,the future state is evaluated.Then,someRC networks are constructed to calculate signal delay.The issues on implementation of signaldelay calculation and construction of RC network delay model are discussed. A computer pro-gram LOMOS (LOgic simulator for MOS digital circuits) is developed.Experiments show thatLOMOS runs two to three orders of magnitude faster than SPICE with delay errors fallingwithin 30% usually.
%K Logic simulation
%K Switch-level model
%K Switchlevel simulation
%K VLSI
%K MOS digital integrated circuits<br>逻辑模拟
%K 开关级模型
%K RC网络
%K IC
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=025C8057C4D37C4BA0041DC7DE7C758F&aid=5D9932CC100F9C31&yid=1833A6AA51F779C1&vid=F3090AE9B60B7ED1&iid=38B194292C032A66&sid=FEF02B4635FE8227&eid=9F6DA927E843CD50&journal_id=1674-4926&journal_name=半导体学报&referenced_num=0&reference_num=1