%0 Journal Article
%T Design of Down Scalers in Mixed-Signal GHz Frequency Synthesizer
%A Xu Yong
%A Wang Zhigong
%A Qiu Yinghua
%A Li Zhiqun
%A Hu Qingsheng
%A Min Rui
%A <br>Xu Yong
%A Wang Zhigong
%A Qiu Yinghu
%A Li Zhiqun
%A Hu Qingsheng
%A and Min Rui
%J 半导体学报
%D 2005
%I 
%X An optimized method is presented to design the down scalers in a GHz frequency synthesizer.The down scalers are comprised of dual modulus prescaler (DMP) and programmable & pulse swallow divider,different methods of high frequency analog circuit and digital logical synthesis are adopted respectively.Using a DMP high speed,lower jitter and lower power dissipation are obtained,and output frequency of 133.0MHz of the DMP working at divide-by-8 shows an RMS jitter less than 2ps.The flexibility and reusability of the programmable divider is high;its use could be extended to many complicated frequency synthesizers.By comparison,it is a better design on performance of high-frequency circuit and good design flexibility.
%K PLL
%K frequency synthesizer
%K dual-modulus prescaler
%K programmable
%K pulse swallow divider<br>PLL
%K frequency
%K synthesizer
%K dual-modulus
%K prescaler
%K programmable
%K &
%K pulse
%K swallow
%K divider
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=025C8057C4D37C4BA0041DC7DE7C758F&aid=507E12A986B089A8&yid=2DD7160C83D0ACED&vid=96C778EE049EE47D&iid=9CF7A0430CBB2DFD&sid=A22DD5EE0F220B37&eid=6FA25BADCDFACCA5&journal_id=1674-4926&journal_name=半导体学报&referenced_num=1&reference_num=6