%0 Journal Article
%T Elevated Source/Drain Engineering by Novel Technology for Fully-Depleted SOI CMOS Devices and Circuits<br>Elevated Source/Drain Engineering by Novel Technology for FullyDepleted SOI CMOS Devices and Circuits
%A LIAN Jun
%A Hai Chaohe
%A <br>Lian
%A Jun
%A an
%A Hai
%A Chaohe
%J 半导体学报
%D 2005
%I 
%X 0.35μm thin-film fully-depleted SOI CMOS devices with elevated source/drain structure are fabricated by a novel technology.Key process technologies are demonstrated.The devices have quasi-ideal subthreshold properties;the subthreshold slope of nMOSFETs is 65mV/decade,while that of pMOSFETs is 69mV/decade.The saturation current of 1.2μm nMOSFETs is increased by 32% with elevated source/drain structure,and that of 1.2μm pMOSFETs is increased by 24%.The per stage propagation delay of 101-stage fully-depleted SOI CMOS ring oscillator is 75ps with 3V supply voltage.
%K FDSOI
%K CMOS
%K elevated source/drain<br>FDSOI
%K CMOS
%K elevated
%K source/drain
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=025C8057C4D37C4BA0041DC7DE7C758F&aid=2042B7DAB79152A6&yid=2DD7160C83D0ACED&vid=96C778EE049EE47D&iid=E158A972A605785F&sid=B7DE0F3CA34DA149&eid=5AE7FA263C8A6D65&journal_id=1674-4926&journal_name=半导体学报&referenced_num=1&reference_num=7