%0 Journal Article
%T A novel nanometer CMOS interconnect optimal model with target delay and bandwidth constraint<br>一种基于延时和带宽约束的纳米级互连线优化模型
%A Zhu Zhang-Ming
%A Hao Bao-Tian
%A Li Ru
%A Yang Yin-Tang
%A <br>朱樟明
%A 郝报田
%A 李儒
%A 杨银堂
%J 物理学报
%D 2010
%I 
%X Optimization of interconnect power and repeater area is an important issue in the design of nanometer CMOS ICs. Based on RLC delay model, the paper proposes a new optimal model to minimize power and area overhead with constraints of target delay and target bandwidth. The proposed model is verified at 90 nm, 65 nm and 45 nm CMOS technology. Experimental result shows that the proposed model can save an average power consumption of 46% and 61% and can save an average area of 65% and 83% at the expense of 1/3 and 1/2 bandwidth, respectively. The proposed optimal model can be used in computer-aided design for nanometer CMOS system-on-chip.
%K nanometer interconnect power
%K repeater area
%K time delay
%K bandwidth<br>纳米互连功耗，
%K 缓冲器面积，
%K 延时，
%K 带宽
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=6E709DC38FA1D09A4B578DD0906875B5B44D4D294832BB8E&cid=47EA7CFDDEBB28E0&jid=29DF2CB55EF687E7EFA80DFD4B978260&aid=678A35C009971BFD4E7141A2CE44131E&yid=140ECF96957D60B2&vid=6AC2A205FBB0EF23&iid=38B194292C032A66&sid=5370399DC954B911&eid=D43C4A19B2EE3C0A&journal_id=1000-3290&journal_name=物理学报&referenced_num=0&reference_num=15