%0 Journal Article
%T 于混合信号片上系统的低相位噪声锁相环设计
%A 矫逸书
%A 周玉梅
%A 蒋见花
%A 吴斌
%J 半导体学报
%D 2010
%I 
%X This paper describes the design of a fully integrated low phase noise CMOS phase-locked loop for mixed-signal SoCs with a wide range of operating frequencies. The design proposes a multi-regulator PLL architecture, in which every noise-sensitive block from the PLL top level is biased from a dedicated linear or shunt regulator, reducing the parasitic noise and spur coupling between different PLL building blocks. Supply-induced VCO frequency sensitivity of the PLL is less than 0.07%-fvco/1%-VDD. The design is fabricated in 0.13 μ m 1.5/3.3 V CMOS technology. The in-band phase noise of –102 dBc/Hz at 1 MHz offset with a spur of less than –45 dBc is measured from 1.25 GHz carrier. The measured RMS jitter of the proposed PLL is 1.72 ps at a 1.25 GHz operating frequency. The total power consumption is 19 mW, and its active area is 0.19 mm2.
%K 锁相环
%K 相位噪声
%K 稳压器
%K 环形振荡器
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=025C8057C4D37C4BA0041DC7DE7C758F&aid=8078745C1B20BEB33EEC1F13DD0DDCB2&yid=140ECF96957D60B2&vid=4AD960B5AD2D111A&iid=9CF7A0430CBB2DFD&sid=2B1E8FE57B9DA3AB&eid=94C357A881DFC066&journal_id=1674-4926&journal_name=半导体学报&referenced_num=0&reference_num=0