%0 Journal Article
%T A 2-GS/s 6-bit self-calibrated flash ADC<br>2GS/s 6-bit 自校准快闪ADC
%A Zhang Youtao
%A Li Xiaopeng
%A Zhang Min
%A Liu Ao
%A Chen Chen
%A <br>张有涛
%A 李晓鹏
%A 张敏
%A 刘奡
%A 陈辰
%J 半导体学报
%D 2010
%I 
%X A single channel 2-GS/s 6-bit ADC with cascade resistive averaging and self foreground calibration is demonstrated in 0.18-μ m CMOS. The calibration method based on DAC trimming improves the linearity and dynamic performance further. The peak DNL and INL are measured as 0.34 and 0.22 LSB, respectively. The SNDR and SFDR have achieved 36.5 and 45.9 dB, respectively, with 1.22 MHz input signal and 2 GS/s. The proposed ADC, including on-chip track-and-hold amplifiers and clock buffers, consumes 570 mW from a single 1.8 V supply while operating at 2 GS/s.
%K analog-to-digital conversion
%K offset averaging
%K flash
%K interpolation
%K calibration<br>模数转换器，失调平均，快闪，内插，校准
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=025C8057C4D37C4BA0041DC7DE7C758F&aid=C40E5549F6BDCE53440EF4965899AA08&yid=140ECF96957D60B2&vid=4AD960B5AD2D111A&iid=9CF7A0430CBB2DFD&sid=9C741045185DEC13&eid=94C357A881DFC066&journal_id=1674-4926&journal_name=半导体学报&referenced_num=0&reference_num=0