%0 Journal Article
%T An 8-bit 180-kS/s differential SAR ADC with a time-domain comparator and 7.97-ENOB<br>一种8-b 180KSPS的带有新颖的时域比较器且有效位数7.97的差分逐次逼近模数转换器
%A Fan Hu
%A Wei Qi
%A Kobenge Sekedi Bomeh
%A Yin Xiumei
%A Yang Huazhong
%A <br>樊华
%A 魏琦
%A Kobenge Sekedi Bomeh
%A 殷秀梅
%A 杨华中
%J 半导体学报
%D 2010
%I 
%X This paper presents a differential successive approximation register analog-to-digital converter (SAR ADC) with a novel time-domain comparator design for wireless sensor networks. The prototype chip has been implemented in the UMC 0.18-μ m 1P6M CMOS process. The proposed ADC achieves a peak ENOB of 7.98 at an input frequency of 39.7 kHz and sampling rate of 180 kHz. With the Nyquist input frequency, 68.49-dB SFDR, 7.97-ENOB is achieved. A simple quadrate layout is adopted to ease the routing complexity of the common-centroid symmetry layout. The ADC maintains a maximum differential nonlinearity of less than 0.08 LSB and integral nonlinearity less than 0.34 LSB by this type of layout.
%K successive approximation register
%K time-domain comparator
%K analog-to-digital converter<br>逐次逼近寄存器
%K 时域比较器
%K 模数转换器
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=025C8057C4D37C4BA0041DC7DE7C758F&aid=9D8AD64E2D99B0A8774012EB4E40C2FF&yid=140ECF96957D60B2&vid=4AD960B5AD2D111A&iid=9CF7A0430CBB2DFD&sid=CFD91C2EE9E88378&eid=94C357A881DFC066&journal_id=1674-4926&journal_name=半导体学报&referenced_num=0&reference_num=0