%0 Journal Article
%T A low-noise PLL design achieved by optimizing the loop bandwidth<br>基于优化环路带宽的低噪声锁相环设计
%A Bai Chuang
%A Zhao Zhenyu
%A Zhang Minxuan
%A <br>白创
%A 赵振宇
%A 张民选
%J 半导体学报
%D 2009
%I 
%X This paper describes a low-noise phase-locked loop (PLL) design method to achieve minimum jitter. Based on the phase noise properties extracted from the transistor, and the low-pass or high-pass transfer characteristics of different noise sources to the o
%K continue-time domain analysis
%K optimal loop bandwidth
%K phase-domain behavioral model
%K timing jitter<br>连续域分析
%K 优化的环路带宽
%K 相位域行为级模型
%K 时域抖动
%U http://www.alljournals.cn/get_abstract_url.aspx?pcid=5B3AB970F71A803DEACDC0559115BFCF0A068CD97DD29835&cid=1319827C0C74AAE8D654BEA21B7F54D3&jid=025C8057C4D37C4BA0041DC7DE7C758F&aid=649396C63D90B2E3385CBCBFF9CB4529&yid=DE12191FBD62783C&vid=340AC2BF8E7AB4FD&iid=5D311CA918CA9A03&sid=7C5F8958E5AC6E60&eid=E158A972A605785F&journal_id=1674-4926&journal_name=半导体学报&referenced_num=0&reference_num=8