%0 Journal Article
%T Error Correction Circuit for Single-Event Hardening of Delay Locked Loops
%A S. Balaji
%A S. Ramasamy
%J Circuits and Systems
%P 2437-2442
%@ 2153-1293
%D 2016
%I Scientific Research Publishing
%R 10.4236/cs.2016.79210
%X In scaled CMOS processes,
the single-event effects generate missing output pulses in Delay-Locked Loop
(DLL). Due to its effective sequence detection of the missing pulses in the
proposed Error Correction Circuit (ECC) and its portability to be applied to
any DLL type, the ECC mitigates the impact of single-event effects and
completes its operation with less design complexity without any concern about losing
the information. The ECC has been implemented in 180 nm CMOS process and
measured the accuracy of mitigation on simulations at LETs up to 100 MeV-cm</span><sup><span style=\"font-size:12px;font-family:Verdana;\">2</span></sup><span style=\"font-size:12px;font-family:Verdana;\">/mg.
The robustness and portability of the mitigation technique are validated
through the results obtained by implementing proposed ECC in XilinxArtix 7
FPGA.
%K Delay-Locked Loop
%K Single Event Transients
%K Error Correction Circuit
%U http://www.scirp.org/journal/PaperInformation.aspx?PaperID=68710