%0 Journal Article
%T Sub-threshold channels at the edges of nanoscale triple-gate silicon transistors
%A H. Sellier
%A G. P. Lansbergen
%A J. Caro
%A N. Collaert
%A I. Ferain
%A M. Jurczak
%A S. Biesemans
%A S. Rogge
%J Physics
%D 2006
%I arXiv
%R 10.1063/1.2476343
%X We investigate by low-temperature transport experiments the sub-threshold behavior of triple-gate silicon field-effect transistors. These three-dimensional nano-scale devices consist of a lithographically defined silicon nanowire surrounded by a gate with an active region as small as a few tens of nanometers, down to 50x60x35 nm^3. Conductance versus gate voltage show Coulomb-blockade oscillations with a large charging energy due to the formation of a small potential well below the gate. According to dependencies on device geometry and thermionic current analysis, we conclude that sub-threshold channels, a few nanometers wide, appear at the nanowire edges, hence providing an experimental evidence for the corner-effect.
%U http://arxiv.org/abs/cond-mat/0603430v2