%0 Journal Article
%T A Substrate-and-Gate Triggering NMOS Device for High ESD Reliability in Deep Submicrometer Technology
%A Chih-Yao Huang
%A Fu-Chien Chiu
%J Advances in Materials Science and Engineering
%D 2013
%I Hindawi Publishing Corporation
%R 10.1155/2013/905686
%X A substrate-and-gate triggering scheme which utilizes dynamic threshold principle is proposed for an ESD NMOS structure. This scheme enhances the device reliability performance in terms of higher second breakdown current and both reduced holding voltage/triggering voltage as well as elimination of gate over driven effect. The simple resistance and RC substrate-and-gate triggering NMOS structure with various resistance/capacitance values totally exhibit superior ESD reliability than the gate-grounded NMOS (GGNMOS) devices by 18~29%. The substrate-and-gate triggering scheme in combination with special substrate pickup styles also shows excellent enhancement when compared with the GGNMOS cases of the same pickup styles. The substrate-and-gate triggering NMOS with butting substrate pickup style is better than the general butting case by 28~30%, whereas the substrate-and-gate triggering NMOS with inserted substrate pickup style is 3.5 times superior to the general inserted case. 1. Introduction Electrostatic discharge (ESD) issue has become a more serious device reliability problem in semiconductor components and systems. An NMOSFET has been the most popular ESD protection candidate for a long time. Since the shrinking of device size advances continually, the ESD capability of the NMOS device encounters more challenges [1¨C7]. A gate-grounded NMOS (GGNMOS) can no longer satisfy the ESD protection mission easily. ESD NMOS protection devices usually need the large width size to deal with ESD events. This results in multifinger layout style which is commonly used in practical IC I/O area. But it also has a critical drawback which is not favorable for the ESD protection requirement. The conduction current is usually unevenly distributed along the width direction of the multifingers. Gate-coupling technique using the property that increases the gate bias can reduce the first trigger point of the NMOS device and enable uniform ESD current distribution [4, 8, 9]. Although gate-coupling technique can improve the ESD capability, it still has gate overdriven effect if the gate voltage coupled is much larger than its threshold voltage, and this leads to serious ESD degradation. Furthermore, inserted or butting substrate pickups in the source diffusion region of the ESD NMOS device in deep submicrometer technology also degraded ESD reliability seriously. Such layout style has been strictly prohibited in practical ESD design applications by the technology design rules. Therefore, in this work, a new substrate-and-gate triggering (SGT) structure that utilizes dynamic
%U http://www.hindawi.com/journals/amse/2013/905686/