%0 Journal Article
%T Generic System Verilog Universal Verification Methodology Based Reusable Verification Environment for Efficient Verification of Image Signal Processing IPS/SOCS
%A Abhishek Jain
%A Giuseppe Bonanno
%A Hima Gupta
%A Ajay Goyal
%J International Journal of VLSI Design & Communication Systems
%D 2013
%I Academy & Industry Research Collaboration Center (AIRCC)
%X In this paper, we present Generic System Verilog Universal Verification Methodology based ReusableVerification Environment for efficient verification of Image Signal Processing IP¡¯s/SoC¡¯s. With the tightschedules on all projects it is important to have a strong verification methodology which contributes toFirst Silicon Success. Deploy methodologies which enforce full functional coverage and verification ofcorner cases through pseudo random test scenarios is required. Also, standardization of verification flow isneeded. Previously, inside imaging group of ST, Specman (e)/Verilog based Verification Environment forIP/Subsystem level verification and C/C++/Verilog based Directed Verification Environment for SoC LevelVerification was used for Functional Verification. Different Verification Environments were used at IPlevel and SoC level. Different Verification/Validation Methodologies were used for SoC Verification acrossmultiple sites. Verification teams were also looking for the ways how to catch bugs early in the designcycle? Thus, Generic System Verilog Universal Verification Methodology (UVM) based ReusableVerification Environment is required to avoid the problem of having so many methodologies and provides astandard unified solution which compiles on all tools.
%K System Verilog
%K Universal Verification Methodology (UVM)
%K register interface(s)
%K video data interface(s)
%K Universal Verification Component(UVC)
%K register and memory model
%K IP-XACT
%K Incisive Software Extension (ISX)
%K Virtual Register Interface (VRI)
%K Verification Abstraction Layer(VAL)
%K UVM-ML.
%U http://airccse.org/journal/vlsi/papers/3612vlsics02.pdf