%0 Journal Article
%T VLSI Based Combined Multiplier Architecture
%A M. Jeevitha
%A R. Muthaiah
%J Journal of Artificial Intelligence
%D 2013
%I Asian Network for Scientific Information
%X In this study, an efficient design of multiplier is been designed. Since multipliers are the basic component in most of the electronic devices. A combination of multiplier is proposed based on the certain parameters in which VLSI design should concentrates, such as area, speed and power. This combination of multipliers is composed of two parts one is carry save array multiplier which concentrates in power dissipation by skipping the blocks when it is not needed. The second part is modified Booth Wallace tree multiplier which concentrates in the speed of the multiplier. This combination is found to produce better results in power and speed parameters resulting in an efficient multiplier design.
%K power
%K speed
%K Multipliers
%K carry save array multiplier
%K modified Booth-Wallace tree multiplier
%U http://docsdrive.com/pdfs/ansinet/jai/2013/145-153.pdf