%0 Journal Article %T Low Power testing by don¡¯t care bit filling technique %A Chetan Sharma %J International Journal of Computer Trends and Technology %D 2011 %I Seventh Sense Research Group %X Test power is major issue of recent scenario of VLSI testing. There are many test pattern generation techniques for testing of combinational circuits with different tradeoffs. The don¡¯t care bit filling method can be used for effective test data compression as well as reduction in scan power. This paper gives a new advancement in automatic test pattern generation method by feeling don¡¯t care bit of the test vector to optimize the switching activities. Finally this concept produces low power testing %K ATPG test vector generation %K Huffman code %K Parity bit generation %K Switching activity %U http://www.ijcttjournal.org/volume-2/issue-1/IJCTT-V2I1P115.pdf