%0 Journal Article
%T Jitter Analysis of Continuous -Time Sigma -Delta Wideband ADC for Software Defined Radio
%A Gulrej Ahmed
%A Dr.R.K.Baghel
%J International Journal of Engineering Science and Technology
%D 2010
%I Engg Journals Publication
%X The Analog-to-Digital-Converter (ADC) constitutes a necessary component for the implementation of Software 每 Defined- Radio (SDR) receiver. In ADC, sampling performance is limited by a clock. The sampling inserts the jitter noise, which degrades the performance of the receiver. Continuous每Time (CT) Delta每Sigma (忖曳) modulators arecapable of suppressing this noise but the impact of clock jitter at the output of the Digital每 to每Analog Converter (DAC) in the feedback path of the modulator should be taken into account. This paper presents an analytical approach for analyzing jitter in SDR receivers when a CT每忖曳 modulator is utilized for Analog每to每Digital Conversion (ADC).
%K ADC
%K SDR
%K CT- 忖曳 modulator
%K Jitter.
%U http://www.ijest.info/docs/IJEST10-02-09-74.pdf