%0 Journal Article
%T Higher test pattern compression for scan based test vectors using weighted bit position method
%A S. Saravanan
%A R. Vijay Sai
%A Har Narayan Upadhyay
%J Journal of Engineering and Applied Sciences
%D 2012
%I Asian Research Publishing Network (ARPN)
%X Present System on Chip (SOC) complexity has brought new challenges in volume of test pattern, low power testing and area complexity. This also shows that implementing huge test pattern and its corresponding storage space are the major problems. Due to this large number of test patterns the data transition time is also increased. This paper considers this problem in scan based test pattern. This proposed approach is based on the compression of huge test pattern by weighted bit position. Test patterns with unspecified bits are considered for specified values and partitioned into necessary weighted value. Depending upon weighted bit position specified test bit is compressed. This in turn reduces the test pattern for scan based testing. The proposed technique tested on ISCAS89 shows significant compression achieved on scan based test pattern.
%K test pattern
%K scan
%K compression
%K weighted bit position
%K partition group.
%U http://www.arpnjournals.com/jeas/research_papers/rp_2012/jeas_0312_649.pdf