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A New UWB Pulse Design Algorithm for Inband Interference Suppression
带内干扰抑制的超宽带脉冲设计

Guo Feng,Zhuang Yiqi,
郭锋
,庄奕琪

光子学报 , 2006,
Abstract: Using the combination of Gaussian monocycles pulse wi th different amplitude and different delay,a new ultra-wideband(UWB) pulse desi gn algorithm for Inband(narrowband or wideband) interference suppression is pres ented.With a Wireless Personal Area Network(WPAN) Communications short duration and a simple implement,the obtained UWB pulse not only meet Federal Communicatio ns Commission(FCC)spectral mask,but dramatically suppress the mutual interferenc es and successfully solves the coexistence problem between UWB system and others existing communication system.Compare with other pulse shapes,our pulse can car ry more energy.In the end,the communication performance of the UWB pulse in the paper and the optimal Gaussian-based monocycle is compared,our pulse have an ob vious advantage over the optimal Gaussian-based monocycle.
An embeddable SOC real-time prediction technology for TDDB
嵌入式SOC栅氧经时击穿实时预报电路与方法

Xin Weiping,Zhuang Yiqi,Li Xiaoming,
辛维平
,庄奕琪,李晓明

半导体学报 , 2012,
Abstract: This paper presents an embeddable SOC real-time prediction circuit and method for TDDB. When the SOC under test is fails due to TDDB, the prediction circuit is capable of issuing a warning signal. The prediction circuit, designed by using a standard CMOS process, occupies a small silicon area and does not share any signal with the circuits under test, therefore, the possibility of interference with the surrounding circuits is safely excluded.
New analytical threshold voltage model for halo-doped cylindrical surrounding-gate MOSFETs
一种新的Halo掺杂圆柱围栅MOSFET阈值电压解析模型

Li Cong,Zhuang Yiqi,Han Ru,
李聪
,庄奕琪,韩茹

半导体学报 , 2011,
Abstract: Using exact solution of two-dimensional Poisson equation in cylindrical coordinates, a new analytical model comprising electrostatic potential, electric field and threshold voltage for halo-doped surrounding-gate MOSFETs is developed. It is found that new analytical model exhibits higher accuracy than that based on parabolic potential approximation when the thickness of silicon channel is much larger than that of the oxide. It is revealed that moderate halo doping concentration, thin gate oxide thickness and small silicon channel radius are needed to improve threshold voltage characteristics. The derived analytical model agrees well with three-dimensional numerical device simulator ISE.
A Method for Locating the Position of an Oxide Trap in a MOSFET by RTS Noise
利用RTS噪声确定MOSFET氧化层中陷阱位置的方法

Bao Li,Bao Junlin,Zhuang Yiqi,
鲍立
,包军林,庄奕琪

半导体学报 , 2006,
Abstract: 强场诱生并与电场奇异性相关的边界陷阱是影响深亚微米MOS器件可靠性的关键因素之一.文中研究了深亚微米MOS器件的随机电报信号(RTS)的时间特性,提出了一种通过正反向测量器件非饱和区噪声的手段来确定边界陷阱空间分布的新方法.对0.18μm×0.15μm nMOS器件的测量结果表明,利用该方法可以准确计算深亚微米器件氧化层陷阱的二维位置,还为深亚微米器件的可靠性评估提供了一种新的手段.
1/F NOISE AS A PREDICTION OF LONG-TERM DRIFT FOR INTEGRATED OPERTIONAL AMPLIFIERS
集成运算放大器参数时漂的1/f噪声预测方法

Zhuang Yiqi,Sun Qing,Hou Xun,
庄奕琪
,孙青,侯洵

电子与信息学报 , 1996,
Abstract: It is shown from the accelerated lifetime test and noise measurement for integrated operational amplifiers that if their failure is caused by the drift of input bias current or input offset current, the drift is strongly correlated with 1/f noise current in these devices, and both are proportional approximately. In the mechanism analysis, the drift may be attributed to the slow capture effect of oxide traps, which are 1/f noise sources, on the electrons in silicon. Therefore, 1/f noise measurement can be used as a fast and non-destructive tool to evaluate the long term instability of integrated operational amplifiers.
A 9.8-mW 1.2-GHz CMOS frequency synthesizer with a low phase-noise LC-VCO and an I/Q frequency divider
一种9.8-mW 1.2-GHz CMOS 低噪声正交输出频率综合器

Li Zhenrong,Zhuang Yiqi,Li Bing,Jin Gang,
李振荣
,庄奕琪,李兵,靳刚

半导体学报 , 2011,
Abstract: A 1.2GHz frequency synthesizer integrated in a RF receiver for Beidou navigation is implemented in standard 0.18μm CMOS technology. A distributed biased varactor LC voltage-controlled oscillator (VCO) is employed to achieve low tuning sensitivity and optimized phase noise performance. A high-speed and low-switching-noise divider-by-2 circuit based on source-coupled logic (SCL) structure is adopted to generate quadrature (I/Q) local oscillating (LO) signal. A high-speed 8/9 dual-modulus prescaler (DMP), a programmable-delay phase frequency detector (PFD) without dead-zone problem, and a programmable-current charge pump (CP) are also integrated in the frequency synthesizer. The frequency synthesizer demonstrates an output frequency from 1.05 to 1.30GHz, and the phase noise is -98.53dBc/Hz at 100-kHz offset and -121.92dBc/Hz at 1-MHz offset from the carrier frequency of 1.21GHz. The power dissipation of core circuits without the output buffer is 9.8mW from a 1.8V power supply. The total area of the receiver is 2.41.6 mm2.
A Low-Voltage, High Efficiency Power Generation Structure for UHF RFID
一种用于UHF RFID的低压高效电源产生电路

Pang Zegui,Zhuang Yiqi,Li Xiaoming,Li Jun,
庞则桂
,庄奕琪,李小明,李俊

半导体学报 , 2008,
Abstract: 介绍了一种为无源UHF RFID设计的高效高灵敏度电源产生电路.该电路基于0.18μm工艺,其中包含了两个电荷泵,一个参考电流源和一组偏置电路.由于其偏置电路消除了传统电路中的阈值损失和体效应,使该电路在低压下的电源转换性能得到很大的提高.要为100kΩ负载提供1.5V电源电压,所需最小输入电压为350mV,转换效率为22%.在负载为60kΩ时,最高可以获得29.8%的转换效率.仿真结果表明,新的电路结构比传统的电荷泵具有更优越的性能.
RTS Amplitude of 90nm MOS Devices in Sub-Threshold Region
90nm MOS器件亚阈值区RTS噪声幅度

Bao Li,Zhuang Yiqi,Ma Xiaohua,Bao Junlin,
鲍立
,庄奕琪,马晓华,包军林

半导体学报 , 2007,
Abstract: 研究了SMIC 90nm工艺1.4nm栅厚度0.18μm×0.15μm尺寸nMOS器件随机电报信号(random telegraph signal,RTS)噪声幅度特性.在此基础上,提出了利用扩散流机理来分析亚阈值区RTS噪声的方法,引入了陷阱电荷影响栅电极的电荷分布,进而对沟道电流产生影响的机制.研究表明,该方法不仅符合实验结果,还可以解释RTS幅度的宽范围分布.
Design of a CMOS multi-mode GNSS receiver VCO
一款多模全球导航卫星系统接收机CMOS压控振荡器设计

Long Qiang,Zhuang Yiqi,Yin Yue,Li Zhenrong,
龙强
,庄奕琪,阴玥,李振荣

半导体学报 , 2012,
Abstract: 本文介绍了一款应用在多模全球导航卫星系统中Σ-Δ小数频率合成器的压控振荡器的设计,压控振荡器采用双级积累模式可变电容器件。基于对调谐开关寄生电容的分析,压控振荡器优化了频率覆盖范围和调谐线性度,频率覆盖了GPS和北斗频段。压控振荡器采用了TSMC CMOS 0.18μm工艺,覆盖了GPS L1,BD B1/B2/B3频段的同时采用了线性化调谐技术,优化了相位噪声。恒定的VCO增益特性进一步提供了宽的电压调整范围,提高了环路的稳定性。
Cost-Effective VDMOS and Compatible Process for PDP Scan-Driver IC
用于PDP扫描驱动芯片的低成本VDMOS及其兼容工艺

Li Xiaoming,Zhuang Yiqi,Zhang Li,Xin Weiping,
李小明
,庄奕琪,张丽,辛维平

半导体学报 , 2007,
Abstract: 给出了采用硅外延BCD工艺路线制造的低成本的VDMOS设计,纵向上有效利用17μm厚度的外延层,横向上得到的VDMOS元胞面积为324μm2,工艺上简化为18次光刻,兼容了标准CMOS、双极管和高压p-LDMOS等器件.VDMOS测试管的耐压超过200V,集成于64路170 PDP扫描驱动芯片功率输出部分,通过了LG-model42v6的PDP上联机验证.
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