Publish in OALib Journal

ISSN: 2333-9721

APC: Only $99


Any time

2020 ( 9 )

2019 ( 431 )

2018 ( 525 )

2017 ( 537 )

Custom range...

Search Results: 1 - 10 of 326914 matches for " Usha S. Mehta "
All listed articles are free for downloading (OA Articles)
Page 1 /326914
Display every page Item
Run-Length-Based Test Data Compression Techniques: How Far from Entropy and Power Bounds?—A Survey
Usha S. Mehta,Kankar S. Dasgupta,Niranjan M. Devashrayee
VLSI Design , 2010, DOI: 10.1155/2010/670476
Abstract: The run length based coding schemes have been very effective for the test data compression in case of current generation SoCs with a large number of IP cores. The first part of paper presents a survey of the run length based codes. The data compression of any partially specified test data depends upon how the unspecified bits are filled with 1s and 0s. In the second part of the paper, the five different approaches for “don't care” bit filling based on nature of runs are proposed to predict the maximum compression based on entropy. Here the various run length based schemes are compared with maximum data compression limit based on entropy bounds. The actual compressions claimed by the authors are also compared. For various ISCAS circuits, it has been shown that when the X filling is done considering runs of zeros followed by one as well as runs of ones followed by zero (i.e., Extended FDR), it provides the maximum data compression. In third part, it has been shown that the average test power and peak power is minimum when the don't care bits are filled to make the long runs of 0s as well as 1s. 1. Introduction As a result of the emergence of new fabrication technologies and design complexities, standard stuck-at scan tests are no longer sufficient. The number of tests, corresponding to data volume and test time, increases with each new fabrication process technology just to maintain test quality requirements. Conventional external testing involves storing all test vectors and test response on ATE. But these testers have limited speed, memory, and I/O channels. Testing cannot proceed any faster than the amount of time required to transfer the test data: ?Test time ≥ (amount of test data on tester)/(number of tester channels × tester clock rate) [1]. As a result, some companies are looking for compression well beyond 100X tester cycle reduction [2–4]. The paper is organized as follows. Section 2 describes the test data compression techniques and the qualities of a good technique. Section 3 presents existing run-length-based codes. Section 4 introduces the different methods of do not care bit filling for run-length-based code. Section 5 introduces entropy. Sections 6 and 7 present the experimental results of test data compression and test power with different methods of X filling. Section 8 compares the actual data compression for various methods claimed in literature with maximum possible compression predicted on the basis of entropy. Section 9 analyzes the nature of test data on the basis of various experimental results. Finally conclusions and future work
Weighted Transition Based Reordering, Columnwise Bit Filling, and Difference Vector: A Power-Aware Test Data Compression Method
Usha Mehta,K. S. Dasgupta,N. M. Devashrayee
VLSI Design , 2011, DOI: 10.1155/2011/756561
Abstract: Test data compression is the major issues for the external testing of IP core-based SoC. From a large pool of diverse available techniques for compression, run length-based schemes are most appropriate for IP cores. To improve the compression and to reduce the test power, the test data processing schemes like “don't care bit filling” and “reordering” which do not require any modification in internal structure and do not demand use of any test development tool can be used for SoC-containing IP cores with hidden structure. The proposed “Weighted Transition Based Reordering-Columnwise Bit Filling-Difference Vector (WTR-CBF-DV)” is a modification to earlier proposed “Hamming Distance based Reordering—Columnwise Bit Filling and Difference vector.” This new method aims not only at very high compression but also aims at shift in test power reduction without any significant on-chip area overhead. The experiment results on ISCAS89 benchmark circuits show that the test data compression ratio has significantly improved for each case. It is also noteworthy that, in most of the case, this scheme does not involve any extra silicon area overhead compared to the base code with which it used. For few cases, it requires an extra XOR gate and feedback path only. As application of this scheme increases run length of zeroes in test set, as a result, the number of transitions during scan shifting is reduced. This may lower scan power. The proposed scheme can be easily integrated into the existing industrial flow. 1. Introduction The testing cost and testing power are the two well-known issues of current generation IC testing [1]. The test cost is directly related to test data volume and hence test data transfer time [2]. Test data compression can solve the problem of test cost by reducing the test data transfer time. The dynamic test power plays a major role in overall test power. The switching activity during test has a large contribution in dynamic power and hence in overall test power. The extensive use of IP cores in SoC has further exaggerated the testing problem. Because of the hidden structure of IP cores, the SoCs containing large IP cores can use only those test data compression techniques and switching reduction technique which do not require any modification or insertion in architecture of IP core. These methods should not also demand the use of ATPG, scan insertion, or any such testing tools. They should be capable to use ready-to-use test data coming with IP core for data compression and power reduction. This test data may be partially specified or fully
Analysis of Test Data Compression Techniques Based on Complementary Huffman Coding
Kinjal A. Bhavsar,,Prof.Usha S.Mehta
International Journal of Engineering Science and Technology , 2011,
Abstract: In this paper we describe the complementary Huffman encoding technique for test data compression for SOC.In this method we use complementary correlations between two blocks which can reduce size of Huffman tree compare to full Huffman but higher compare to selective and optimal Huffman coding and also increase compression ratios compare to selective and Huffman coding methods. Test application timeis higher compare to full Huffman and less compare to selective and optimal selective Huffman coding.
The Kleeblattschadel (cloverleaf skull) syndrome
Ghose Supriyo,Mehta Usha
Indian Journal of Ophthalmology , 1986,
Implementation of Compaction Algorithm for ATPG Generated Partially Specified Test Data
Vaishali Dhare,Usha Mehta
International Journal of VLSI Design & Communication Systems , 2013,
Abstract: n this paper the ATPG is implemented using C++. This ATPG is based on fault equivalence concept inwhich the number of faults gets reduced before compaction method. This ATPG uses the line justificationand error propagation to find the test vectors forreduced fault set with the aid of controllability andobservability. Single stuck at fault model is considered. The programs are developed for fault equivalencemethod, controllability Observability, automatic test pattern generation and test data compaction usingobject oriented language C++. ISCAS 85 C17 circuitwas used for analysis purpose along with othercircuits. Standard ISCAS (International Symposium on Circuits And Systems) netlist format was used. Theflow charts and results for ISCAS 85 C17 circuits along with other netlists are given in this paper. The testvectors generated by the ATPG further compacted toreduce the test vector data. The algorithm isdeveloped for the test vector compaction and discussed along with result
Instant-Form and Light-Front Hamiltonian and Path Integral Formulations of the Conformally Gauge-Fixed Polyakov D1-Brane Action in the Presence of a Scalar Axion Field and an U(1) Gauge Field  [PDF]
Usha Kulshreshtha, Daya S. Kulshreshtha
Journal of Modern Physics (JMP) , 2013, DOI: 10.4236/jmp.2013.44A009

Recently we have studied the instant-form quantization (IFQ) and the light-front quantization (LFQ) of the conformally gauge-fixed Polyakov D1 brane action using the Hamiltonian and path integral formulations. The IFQ is studied in the equal world-sheet time framework on the hyperplanes defined by the world-sheet time σ0=τ=constant and the LFQ in the equal light-cone world-sheet time framework, on the hyperplanes of the light-front defined by the light-cone world-sheet time σ+= (τ+σ) =constant. The light-front theory is seen to be a constrained system in the sense of Dirac in contrast to the instant-form theory. However, owing to the gauge anomalous nature of these theories, both of these theories are seen to lack the usual string gauge symmetries defined by the world-sheet reparametrization invariance (WSRI) and the Weyl invariance (WI). In the present work we show that these theories when considered in the presence of background gauge fields such as the NSNS 2-form gauge field Bαβ(σ,τ) or in the presence of U(1) gauge field A

Suitability of Various Low-Power Testing Techniques for IP Core-Based SoC: A Survey
Usha Mehta,Kankar Dasgupta,Niranjan Devashrayee
VLSI Design , 2011, DOI: 10.1155/2011/948926
Abstract: Test power is the major issue for current generation VLSI testing. It has become the biggest concern for today's SoC. While reducing the design efforts, the modular design approach in SoC (i.e., use of IP cores in SoC) has further exaggerated the test power issue. It is not easy to select an effective low-power testing strategy from a large pool of diverse available techniques. To find the proper solutions for test power reduction strategy for IP core-based SoC, in this paper, starting from the terminology and models for power consumption during test, the state of the art in low-power testing is presented. The paper contains the detailed survey on various power reduction techniques proposed for all aspects of testing like external testing, Built-In Self-Test techniques, and the advances in DFT techniques emphasizing low power. Further, all the available low-power testing techniques are strongly analyzed for their suitability to IP core-based SoC. 1. Introduction The power consumption has been a major challenge to both design and test engineers. The efforts to reduce the power consumption during normal function mode further exaggerated the power consumption problem during test. Generally, a circuit may consume 3–8 times power in the test mode than in the normal mode [1]. As a result, the semiconductor industry is looking for low-power testing techniques [2]. To reduce the cost and time to market, the modular design approach is largely adopted for SoC. The structure of such predesigned, ready-to-use intellectual property (IP) core is often hidden from the system integrator. So testing of such cores is even more daunting. So power reduction during testing of such cores puts many constraints on current low-power testing methodology. To develop the right testing strategy for such SoC, it is necessary to survey all the available low-power testing approaches and find out the suitable approach for such SoC. The paper is organized as follows. Section 2 gives the reasons for very high-power consumption during test and its effects of such high-power consumption on IC. It also includes definitions of various terms related to test power and also explains the model for energy and power. Section 3 contains the various schemes for low-power testing. Section 4 discusses the suitability of each scheme with reference to IP core-based SoC. Section 5 concludes the survey and explores the future scope. 2. Low-Power Test A high density system like ASIC or SoC always demands the nondestructive test which satisfies all the power constraints defined during design phase. On the
Clonidine in angle closure glaucoma
Mehta Usha,Agarwal H,Sood N
Indian Journal of Ophthalmology , 1985,
Clonidine in chronic simple glaucoma
Mehta Usha,Agarwal H,Sood N
Indian Journal of Ophthalmology , 1985,
Approximate Solution of Non-Linear Reaction Diffusion Equations in Homogeneous Processes Coupled to Electrode Reactions for CE Mechanism at a Spherical Electrode  [PDF]
A. Eswari, S. Usha, L. Rajendran
American Journal of Analytical Chemistry (AJAC) , 2011, DOI: 10.4236/ajac.2011.22010
Abstract: A mathematical model of CE reaction schemes under first or pseudo-first order conditions with different diffusion coefficients at a spherical electrode under non-steady-state conditions is described. The model is based on non-stationary diffusion equation containing a non-linear reaction term. This paper presents the complex numerical method (Homotopy perturbation method) to solve the system of non-linear differential equation that describes the homogeneous processes coupled to electrode reaction. In this paper the approximate analytical expressions of the non-steady-state concentrations and current at spherical electrodes for homogeneous reactions mechanisms are derived for all values of the reaction diffusion parameters. These approximate results are compared with the available analytical results and are found to be in good agreement.
Page 1 /326914
Display every page Item

Copyright © 2008-2017 Open Access Library. All rights reserved.