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Search Results: 1 - 10 of 145 matches for " Tourki Rached "
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Race-Free State Assignment Technique for Asynchronous Circuits
Abdelkrim Zitouni,Rached Tourki
International Journal of Electrical and Power Engineering , 2012,
Abstract: One of the most growing areas in circuit design is asynchronous circuit’s design. These circuits incorporate a number of hazard problems such as race. The multitude of the different techniques that have been proposed to avoid race problems in an asynchronous circuit can be classified into two major types: The techniques belonging to the first type yield large circuits with low power dissipation and the techniques belonging to the second type yield relatively small circuits with high power dissipation. The majority of these techniques are NP-complete and require extremely large computation times for large flow table. This study considers the state assignment problem for circuits operating in the normal fundamental mode and describes a new procedure especially suited to the automated synthesis of large circuits. The proposed technique constitutes a trade-off between silicon area and power dissipation.
Efficient Hardware/Software Implementation of LPC Algorithm in Speech Coding Applications  [PDF]
Mohamed Atri, Fatma Sayadi, Wajdi Elhamzi, Rached Tourki
Journal of Signal and Information Processing (JSIP) , 2012, DOI: 10.4236/jsip.2012.31016
Abstract: The LPC “Linear Predictive Coding” algorithm is a widely used technique for voice coder. In this paper we present different implementations of the LPC algorithm used in the majority of voice decoding standard. The windowing/autocorrelation bloc is implemented by three different versions on an FPGA Spartan 3. Allowing the possibility to integrate a Microblaze processor core a first solution consists of a pure software implementation of the LPC using this core RISC processor. Second solution is a pure hardware architecture implemented using VHDL based methodology starting from description until integration. Finally, the autocorrelation core is then proposed to be implemented using hardware/software (HW/SW) architecture with the existing processor. Each architecture performances are compared for different data lengths.
A Blind Watermarking Algorithm Implementation for Digital Images and Video
Sourour Karmani,Ridha Djemal,Rached Tourki
International Journal of Soft Computing , 2012,
Abstract: With the growth of new image technologies, copyright protection becomes an important issue to preserve digital images and video properties. In this paper, we propose an improved implementation of a blind object watermarking scheme for images and video streams. To make the watermark robust and perceptual invisible, we have used a two dimensional wavelet transform as a transformation domain for both image and watermark. We have also used an optimized quantization and replacement strategies within the insertion process. A hardware architecture is designed and tested in order to evaluate the performance of our proposed watermarking algorithm. This architecture has been implemented on the Altera Stratix II prototyping board.
Data traffic load balancing and QoS in IEEE 802.11 network: Experimental study of the signal strength effect
Adel Soudani,Thierry Divoux,Rached Tourki
Computer Science , 2012, DOI: 10.1016/j.compeleceng.2012.07.016
Abstract: The performances of multimedia applications built on wireless systems depend on bandwidth availability that might heavily affect the quality of service. The IEEE 802.11 standards do not provide performed mechanism for bandwidth management through data load distribution among different APs of the network. Then, an AP can be heavily overloaded causing throughput degradation. Load Balancing Algorithms (LBAs) was been considered as one of the attractive solution to share the traffic through the available access points bandwidths. However, applying the load balancing algorithm and shifting a mobile connection from an access point to another without considering the received signal strength indicator of the concerned APs might causes worst communication performances. This paper is a contribution to check the performance's limits of the LBA algorithm through experimental evaluation of communication metrics for MPEG-4 video transmission over IEEE 802.11 network. Then, the paper focuses on the proposition of a new LBA algorithm structure with the consideration of the RSS level.
Experimental Performances Analysis of Load Balancing Algorithms in IEEE 802.11
Hamdi Salah,Soudani Adel,Tourki Rached
Computer Science , 2009,
Abstract: In IEEE 802.11, load balancing algorithms (LBA) consider only the associated stations to balance the load of the available access points (APs). However, although the APs are balanced, it causes a bad situation if the AP has a lower signal length (SNR) less than the neighbor APs. So, balance the load and associate one mobile station to an access point without care about the signal to noise ratio (SNR) of the AP cause possibly an unforeseen QoS, such as the bit rate, the end to end delay, the packet loss. In this way, we study an improvement load balancing algorithm with SNR integration at the selection policy.
A New Generic GALS Router with Multiple QoS for NoC
Abdelkrim Zitouni,Mounir Zid,Mejdi Kerkeni,Sami Badrouchi,Rached Tourki
International Journal of Soft Computing , 2012,
Abstract: In the System on Chip (SoC) design, the synthesis of communication architecture constitutes the bottleneck which can affect the performances of the system. The Quality of Service Network on Chip (QNoC) is the most perferment solution that provides low latency transfers and power efficient System on Chip (SoC) interconnect. This study presents new asynchronous and generic router (GeRouter) for use in the new NoC generation architectures (Spider, Polygon, Octagon, etc). This router integrates a generic number of interconnected input and output ports, a sophisticated speed independent dynamic arbiter; a CRC based checking scheme, an Aloha retransmission protocol and two different routing techniques (Wormhole and Virtual Cut Through). This makes it possible to improve the Quality of Service (QoS) required by the NoC that integrate it. The performance study show that the proposed router enables higher data rate and low latency transfers.
A Novel Positioning Technique with Low Complexity in Wireless LAN: Hardware implementation
Monji ZAIDI,Ridha OUNI,Jamila Bhar,Rached TOURKI
Lecture Notes in Engineering and Computer Science , 2011,
Abstract:
DESIGN OF RECONFIGURABLE IMAGE ENCRYPTION PROCESSOR USING 2-D CELLULAR AUTOMATA GENERATOR.
Machhout Mohsen,Guitouni Zied,Zeghid Medien,Tourki Rached
International Journal of Computer Science & Applications , 2009,
Abstract:
A Comparative Study of Power Consumption Models for CPA Attack
Hassen Mestiri,Noura Benhadjyoussef,Mohsen Machhout,Rached Tourki
International Journal of Computer Network and Information Security , 2013,
Abstract: Power analysis attacks are types of side channel attacks that are based on analyzing the power consumption of the cryptographic devices. Correlation power analysis is a powerful and efficient cryptanalytic technique. It exploits the linear relation between the predicted power consumption and the real power consumption of cryptographic devices in order to recover the correct key. The predicted power consumption is determined by using the appropriate consumption model. Until now, only a few models have been proposed and used.In this paper, we describe the process to conduct the CPA attack against AES on SASEBO-GII board. We present a comparison between the Hamming Distance model and the Switching Distance model, in terms of number of power traces needed to recover the correct key using these models. The global successful rate achieves 100% at 11100 power traces. The power traces needed to recover the correct key have been decreased by 12.6% using a CPA attack with Switching Distance model.
Low Power Elliptic Curve Digital Signature Design for Constrained Devices
Elhadjyoussef Wajih,Benhadjyoussef Noura,Machhout Mohsen,Tourki Rached
International Journal of Security , 2012,
Abstract: Digital signatures represent one of the most widely used security technologies for ensuringunforgeability and non-repudiation of digital data. In this paper a reduced power dissipation ofhardware Elliptic Curve Digital Signature design has been developed.Our proposed architecture is based on the Globally Asynchronous Locally Synchronous (GALS)design methodology. In GALS system, modules that are not used frequently can be made toconsume less power by pausing their local clocks until they are needed. Our design consists ofusing units that are clocked independently. The whole ECDSA design is captured using VHDLlanguage, over the finite field GF (2163), and the Virtex IV FPGA device is used for the hardwareimplementation of the architecture.
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