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Quantum-dot cellular automaton (QCA) is an emerging, promising, future generation nanoelectronic computational architecture that encodes binary information as electronic charge configuration of a cell. It is a digital logic architecture that uses single electrons in arrays of quantum dots to perform binary operations. Fundamental unit in building of QCA circuits is a QCA cell. A QCA cell is an elementary building block which can be used to build basic gates and logic devices in QCA architectures. This paper evaluates the performance of various implementations of QCA based XOR gates and proposes various novel layouts with better performance parameters. We presented the various QCA circuit design methodology for XOR gate. These layouts show less number of crossovers and lesser cell count as compared to the conventional layouts already present in the literature. These design topologies have special functions in communication based circuit applications. They are particularly useful in phase detectors in digital circuits, arithmetic operations and error detection & correction circuits. The comparison of various circuit designs is also given. The proposed designs can be effectively used to realize more complex circuits. The simulations in the present work have been carried out using QCADesigner tool.
This paper investigates the threshold voltage sensitivity to metal gate work-function for n-channel double gate fin field-effect transistor (FinFET) structures and evaluates the short channel performance of the device using threshold voltage dependence on metal gate work-function analysis. We carried out the study for a double gate n-channel fin field-effect transistor (n-FinFET) with parameters as per the projection report of International Technology Roadmap for Semiconductors, ITRS-2011 for low standby power (LSTP) 20 nm gate length technology node. In the present study device simulation have been carried out using PADRE simulator from MuGFET, which is based on the drift-diffusion theory. Our results show the accuracy and validity of classical drift-diffusion simulation results for transistor structures with lateral dimensions 10nm and above. The subthreshold behavior of device improves with increased metal gate work-function. The results also show that a higher gate work-function (≥5 eV) can fulfill the tolerable off-current as projected in ITRS 2011 report. The SCE in FinFET can reasonably be controlled and improved by proper adjustment of the metal gate work-function. DIBL is reduced with the increase in gate work function.