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Search Results: 1 - 10 of 401461 matches for " M. Glesner "
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Resonance circuits for adiabatic circuits
C. Schlachta,M. Glesner
Advances in Radio Science : Kleinheubacher Berichte , 2003,
Abstract: One of the possible techniques to reduces the power consumption in digital CMOS circuits is to slow down the charge transport. This slowdown can be achieved by introducing an inductor in the charging path. Additionally, the inductor can act as an energy storage element, conserving the energy that is normally dissipated during discharging. Together with the parasitic capacitances from the circuit a LCresonant circuit is formed.
Results and limits in the 1-D analytical modeling for the asymmetric DG SOI MOSFET
O. Cobianu,M. Glesner
Advances in Radio Science : Kleinheubacher Berichte , 2008,
Abstract: This paper presents the results and the limits of 1-D analytical modeling of electrostatic potential in the low-doped p type silicon body of the asymmetric n-channel DG SOI MOSFET, where the contribution to the asymmetry comes only from p- and n-type doping of polysilicon used as the gate electrodes. Solving Poisson's equation with boundary conditions based on the continuity of normal electrical displacement at interfaces and the presence of a minimum electrostatic potential by using the Matlab code we have obtained a minimum potential with a slow variation in the central zone of silicon with the value pinned around 0.46 V, where the applied VGS voltage varies from 0.45 V to 0.95 V. The paper states clearly the validity domain of the analytical solution and the important effect of the localization of the minimum electrostatic potential value on the potential variation at interfaces as a function of the applied VGS voltage.
Hardware implementation of smart antenna systems
H. Wang,M. Glesner
Advances in Radio Science : Kleinheubacher Berichte , 2006,
Abstract: Smart antenna systems attract a lot attentions now and believably more in the future, as it can increase the capacity of mobile communication systems dramatically. Design of smart antenna systems combines the technologies of antenna design, signal processing, and hardware implementation. In this paper, a propose of smart antenna structure, as well as some function blocks that have been already implemented in hardware will be presented.
Resolving longitudinal amplitude and phase information of two continuous data streams for high-speed and real-time processing
A. Guntoro,M. Glesner
Advances in Radio Science : Kleinheubacher Berichte , 2009,
Abstract: Although there is an increase of performance in DSPs, due to its nature of execution a DSP could not perform high-speed data processing on a continuous data stream. In this paper we discuss the hardware implementation of the amplitude and phase detector and the validation block on a FPGA. Contrary to the software implementation which can only process data stream as high as 1.5 MHz, the hardware approach is 225 times faster and introduces much less latency.
A Verilog-A model of an undoped symmetric dual-gate MOSFET
O. Cobianu,O. Soffke,M. Glesner
Advances in Radio Science : Kleinheubacher Berichte , 2006,
Abstract: We describe a new procedure of solving the electrostatic potentials in the silicon film of an undoped DG SOI MOSFET structure. Starting from a model previously described in the literature by Malobabic et al. (2004), we propose the bisection method for the solution of transcendental equation giving the surface electrostatic potential of the silicon channel, as a function of the gate to source voltage and the voltage along the channel. The above calculated results are used for obtaining the charges and corresponding drain current in the DG MOSFET transistor. The entire model is implemented in Verilog A and can be used inside Cadence for the determination of the static regime of electrical circuits based on undoped symmetric DG SOI MOSFET. As a case study, a simple common-source amplifier built with such a novel device is analyzed, showing the currents and voltages present in the circuit.
Simulation von CNFET basierten Digitalschaltungen
O. Soffke,P. Zipf,M. Velten,M. Glesner
Advances in Radio Science : Kleinheubacher Berichte , 2006,
Abstract: Einwandige Kohlenstoff Nanor hrchen k nnen sowohl halbleitende als auch metallische Eigenschaften aufweisen, je nachdem wie die R hrchenachse im Vergleich zur Anordnung der Kohlenstoffatome verl uft. Dies wird durch den sogenannten Aufrollvektor bestimmt. Halbleitende Nanor hrchen k nnen für Transistoren (CNFETs) verwendet werden, deren Verhalten sich mit einer modifizierten Version von Berkeley Spice 3f5 simulieren l t. Die aus diesen Simulationen gewonnenen Parameter werden zur Parametrisierung von SystemC Modellen aus CNFETs bestehender Grundschaltungen verwendet, was zu einer um Gr enordnungen h heren Simulationsgeschwindigkeit bei hoher Genauigkeit führt. Single walled carbon nanotubes (CNT) can be either metallic or semiconducting depending on the tube's orientation in relation to the configuration of the carbon atoms. This is determined by the so-called chiral vector. Semiconducting CNT can be used in transistors (CNFET) which can be simulated by a modified version of Berkeley Spice 3f5. The parameters determined by these simulations are used to parameterise SystemC models of some basic building blocks yielding fast simulations with high accuracy.
A curvature-corrected CMOS bandgap reference
O. Mitrea,C. Popa,A. M. Manolescu,M. Glesner
Advances in Radio Science : Kleinheubacher Berichte , 2003,
Abstract: This paper presents a CMOS bandgap reference that employs a curvature correction technique for compensating the nonlinear voltage temperature dependence of a diode connected BJT. The proposed circuit cancels the first and the second order terms in the VBE(T ) expansion by using the current of an autopolarizedWidlar source and a small correction current generated by a MOSFET biased in weak inversion. The voltage reference has been fabricated in a 0.35μm 3Metal/2Poly CMOS technology and the chip area is approximately 70μm × 110μm. The measured temperature coefficient is about 10.5 ppm/K over a temperature range of 10– 90°C while the power consumption is less than 1.4mW.
Towards a Formal Framework for Mobile, Service-Oriented Sensor-Actuator Networks
Helena Gruhn,Sabine Glesner
Electronic Proceedings in Theoretical Computer Science , 2013, DOI: 10.4204/eptcs.108.4
Abstract: Service-oriented sensor-actuator networks (SOSANETs) are deployed in health-critical applications like patient monitoring and have to fulfill strong safety requirements. However, a framework for the rigorous formal modeling and analysis of SOSANETs does not exist. In particular, there is currently no support for the verification of correct network behavior after node failure or loss/addition of communication links. To overcome this problem, we propose a formal framework for SOSANETs. The main idea is to base our framework on the π-calculus, a formally defined, compositional and well-established formalism. We choose KLAIM, an existing formal language based on the π-calculus as the foundation for our framework. With that, we are able to formally model SOSANETs with possible topology changes and network failures. This provides the basis for our future work on prediction, analysis and verification of the network behavior of these systems. Furthermore, we illustrate the real-life applicability of this approach by modeling and extending a use case scenario from the medical domain.
Combining Inclusion Polymorphism and Parametric Polymorphism
Sabine Glesner,Karl Stroetmann
Computer Science , 1999,
Abstract: We show that the question whether a term is typable is decidable for type systems combining inclusion polymorphism with parametric polymorphism provided the type constructors are at most unary. To prove this result we first reduce the typability problem to the problem of solving a system of type inequations. The result is then obtained by showing that the solvability of the resulting system of type inequations is decidable.
Networks-On-Chip Based on Dynamic Wormhole Packet Identity Mapping Management
Faizal A. Samman,Thomas Hollstein,Manfred Glesner
VLSI Design , 2009, DOI: 10.1155/2009/941701
Abstract: This paper presents a network-on-chip (NoC) with flexible infrastructure based on dynamic wormhole packet identity management. The NoCs are developed based on a VHDL approach and support the design flexibility. The on-chip router uses a wormhole packet switching method with a synchronous parallel pipeline technique. Routing algorithms and dynamic wormhole local packet identity (ID-tag) mapping management are proposed to support a wire sharing methodology and an ID slot division multiplexing technique. At each communication link, flits belonging to the same message have the same local ID-tag, and the ID-tag is updated before the packet enters the next communication link by using an ID-tag mapping management unit. Therefore, flits from different messages can be interleaved, identified, and routed according to their allocated ID slots. Our NoC guarantees in order and lossless message delivery.
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