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Search Results: 1 - 10 of 37612 matches for " Jin Young Choi "
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A Comparison Study of Input ESD Protection Schemes Utilizing NMOS, Thyristor, and Diode Devices  [PDF]
Jin Young Choi
Communications and Network (CN) , 2010, DOI: 10.4236/cn.2010.21002
Abstract: For three fundamental input-protection schemes suitable for high-frequency CMOS ICs, which utilize protection devices such as NMOS transistors, thyristors, and diodes, we attempt an in-depth comparison on HBM ESD robustness in terms of lattice heating inside protection devices and peak voltages developed across gate oxides in input buffers, based on DC, mixed-mode transient, and AC analyses utilizing a 2-dimensional device simulator. For this purpose, we construct an equivalent circuit model of input HBM test environments for CMOS chips equipped with input ESD protection circuits, which allows mixed-mode transient simulations for various HBM test modes. By executing mixed-mode simulations including up to six active protection devices in a circuit, we attempt a detailed analysis on the problems, which can occur in real tests. In the procedure, we suggest to a recipe to ease the bipolar trigger in the protection devices and figure out that oxide failure in internal circuits is determined by the peak voltage developed in the later stage of discharge, which corresponds to the junction breakdown voltage of the NMOS structure residing in the protection devices. We explain strength and weakness of each protection scheme as an input ESD protection circuit for high-frequency ICs, and suggest valuable guidelines relating design of the protection devices and circuits.
An Analytical Approach for Fast Automatic Sizing of Narrow-Band RF CMOS LNAs  [PDF]
Jin Young Choi
Circuits and Systems (CS) , 2012, DOI: 10.4236/cs.2012.32018
Abstract: We introduce a fast automatic sizing algorithm for a single-ended narrow-band CMOS cascode LNA adopting an inductive source degeneration based on an analytical approach without any optimization procedure. Analytical expressions for principle parameters are derived based on an ac equivalent circuit. Based on the analytical expressions and the power-constrained noise optimization criteria, the automatic sizing algorithm is developed. The algorithm is coded using Matlab, which is shown capable of providing a set of design variable values within seconds. One-time Spectre simulations assuming usage of a commercial 90 nm CMOS process are performed to confirm that the algorithm can provide the aimed first-cut design with a reasonable accuracy for the frequency ranging up to 5 GHz. This work shows one way how accurate automatic synthesis can be done in an analytical approach.
An Analytical Approach for Fast Automatic Sizing of Narrow-Band RF CMOS LNAs with a Capacitive Load  [PDF]
Jin Young Choi
Circuits and Systems (CS) , 2012, DOI: 10.4236/cs.2012.34045
Abstract: We introduce a fast automatic sizing algorithm for a single-ended narrow-band CMOS cascode LNA with a capacitive load based on an analytical approach without any optimization procedure. Analytical expressions for principle parameters are derived based on an ac equivalent circuit. Based on the analytical expressions and the power-constrained noise optimization criteria, the automatic sizing algorithm is developed. The algorithm is coded using Matlab, which is shown capable of providing a set of design variable values within seconds. One-time Spectre simulations assuming usage of a commercial 90 nm CMOS process are performed to confirm that the algorithm can provide the aimed first-cut design with a reasonable accuracy for the frequency ranging up to 5 GHz.
On a Parasitic Bipolar Transistor Action in a Diode ESD Protection Device  [PDF]
Jin Young Choi
Circuits and Systems (CS) , 2016, DOI: 10.4236/cs.2016.79199
Abstract: In this work, we show that an excessive lattice heating problem can occur in the diode electrostatic discharge (ESD) protection device connected to a VDDbus in the popular diode input protection scheme, which is favorably used in CMOS RF ICs. To figure out the reason for the excessive lattice heating, we construct an equivalent circuit for input human-body model (HBM) test environment of a CMOS chip equipped with the diode protection circuit, and execute mixed-mode transient simulations utilizing a 2-D device simulator. We analyze the simulation results in detail to show out that a parasitic pnp bipolar transistor action relating nearby p+-substrate contacts is responsible for the excessive lattice heating in the diode protection device, which has never been focused before anywhere.
Discharge Characteristics of a Triple-Well Diode-String ESD Clamp  [PDF]
Jin Young Choi
Circuits and Systems (CS) , 2018, DOI: 10.4236/cs.2018.95008
Abstract: In this work, DC and transient characteristics of a 4 diode string utilizing triple-well technologies as a VDD-VSS clamp device for ESD protection are analyzed in detail based on 2-dimensional device and mixed-mode simulations. It is shown that there exists parasitic pnp bipolar transistor action in this device leading to a sudden increase in DC substrate leakage if anode bias is getting high. Through transient simulations for a 2000 V PS-mode HBM ESD discharge event, it is shown that the dominant discharge path is the one formed by a parasitic pnpn thyristor and a parasitic npn bipolar transistor in series. Percentage ratios of the various current components regarding the anode current at its current peaking are provided. The mechanisms involved in ESD discharge inside the diode-string clamp utilizing triple-well technologies are explained in detail, which has never been done anywhere in the literature based on simulations or measurements.
A Thyristor-Only Input ESD Protection Scheme for CMOS RF ICs  [PDF]
Jin Young Choi, Choongkoo Park
Circuits and Systems (CS) , 2011, DOI: 10.4236/cs.2011.23025
Abstract: We propose an input protection scheme composed of thyristor devices only without using a clamp NMOS device in order to minimize the area consumed by a pad structure in CMOS RF ICs. For this purpose, we suggest low-voltage triggering thyristor protection device structures assuming usage of standard CMOS processes, and attempt an in-depth comparison study with a conventional thyristor protection scheme incorporating a clamp NMOS device. The comparison study mainly focuses on robustness against the HBM ESD in terms of peak voltages applied to gate oxides in an input buffer and lattice heating inside protection devices based on DC and mixed-mode transient analyses utilizing a 2-dimensional device simulator. We constructed an equivalent circuit for the input HBM test environment of the CMOS chip equipped with the input ESD protection devices. And by executing mixed-mode simulations including up to four protection devices and analyzing the results for five different test modes, we attempt a detailed analysis on the problems which can occur in real HBM tests. We figure out strength of the proposed thyristor-only protection scheme, and suggest guidelines relating the design of the protection devices and circuits.
Mapping out the social experience of cancer patients with facial disfigurement  [PDF]
Alessandro Bonanno, Jin Young Choi
Health (Health) , 2010, DOI: 10.4236/health.2010.25063
Abstract: This article contributes to the limited literature on the social consequences of cancer generated facial disfigurement by reporting the result of an exploratory analysis of interaction between facially disfigured cancer patients and strangers and acquaintances (secondary groups). Secondary groups are those in which membership occurs due to performance of formal and/or non-intimate roles. Interaction is studied as it takes place in different social settings. Indivi- duals who are affected by cancer of the head and neck region can now expect to survive for many years after the cancer is detected and later surgically removed. Because of surgery, these survivors live the rest of their lives with facial disfigurement and are stigmatized and socially excluded. It follows that a new and socially relevant situation has emerged: as medicine develops and allows more patients to survive, it forces them to spend significant portions of their lives dealing with the stigma associated with facial disfigurement. Research on social issues pertaining to facially disfigured cancer patients remains sparse. Limited knowledge has been produced on the “social context” within which interaction between the disfigured and relevant social groups takes place. To date most research has focused on the individual and his/her ability to adapt to the condition of facially disfigured. To address this scientific gap and document the manner through which the interaction process is socially created and evolves, interviews with fourteen facially disfigured cancer patients were carried out. These interviews were designed to reconstruct the interaction experiences of these individuals in different social contexts. Data were analyzed through the qualitative approach of grounded theory. Results indicate that patients can be divided into two groups: Occasionally Comfortable Patients and Always Comfortable Patients. Occasionally comfortable patients are individuals who experience different levels of comfort in interaction. In some situations they do not feel stigmatized, but other interactions constitute the contexts within which this discomfort emerges. Discomfort in interaction was employed as an indicator of stigmatization. Interacting groups were divided into small and large. Intrusion (unsolicited attention to patients) in interaction in large and small groups always generates uncomfortable situations. Sympathy (unsolicited comments and/or actions in support of patients) is associated with comfort in interaction in small groups and produces varying patterns in the case of large groups.
The Community Structure of Macrozoobenthos and Its Temporal Change on the Gapo Artificial Tidal Flat in Masan Bay, Korea  [PDF]
Jin-Woo Choi, Jin-Young Seo, Soonmo An
Open Journal of Marine Science (OJMS) , 2013, DOI: 10.4236/ojms.2013.34022
Abstract:

This study was conducted to get some basic information on the community structure of macrozoobenthos and its temporal change at 3 sites on the Gapo artificial tidal flat within Masan Bay from March 2002 to April 2004 when 8 years passed after the construction. The Gapo artificial tidal flat was constructed by filling the dredged contaminated sediments of MasanBayfrom 1990 to 1993. The surface sediment consisted of fine particles, but the grain size at the tidal flat has changed from mud to muddy sand by adding coarse particles for manila clam aquaculture by local fishermen from 2002. A total of 35 faunal species including 23 species at the upper tidal flat, 28 species at the lower tidal flat and 30 species in the tidal channel were collected during the study period. Polychaete worms were the most dominant fauna in species number and total faunal density, but mollusks were the most dominant in biomass. There was a specific species composition along tidal level. At the upper tidal flat, Prionospio japonicus, Sigambra tentaculata, and Neanthes succinea were dominant and at the lower tidal flat, N. succinea, P. japonicus, Corophium sinensis, and Ruditapes philipinarum were dominant while

A Comparison Study of Diode-String ESD Clamps for CMOS Input Protection  [PDF]
Jin Young Choi
Circuits and Systems (CS) , 2019, DOI: 10.4236/cs.2019.102002
Abstract: Based on 2-D device simulations and mixed-mode transient simulations, DC and transient discharge characteristics of a usual diode string utilizing a standard CMOS process, and a diode string utilizing a triple-well CMOS process, which can serve as an essential VDD-VSS clamp device for CMOS input ESD protection were compared. Transient discharge characteristics including peak voltages developed across gates oxides of transistors in input buffers, lattice heating inside ESD protection devices, and ratios of discharge current components at its peak inside the diode-string clamp were compared. DC standby current levels added per each input pad structure, which are the critical parameters determining usefulness of the devices, were also compared. We showed that the diode-string devices in comparison can serve successfully as a VDD-VSS clamp device for ESD protection by virtue of the dominant pnpn thyristor-related conduction mechanisms. Optimization of design parameters including anode-cathode contact spacing in each diode in the string, device width of the diode string, and number of diodes in the diode string was performed to present transient discharge and DC characteristics of some recommendable design examples, which can serve as a guideline in designing diode-string clamp devices.
The PL Characteristics of ZnO Thin Film on Flexible Polymer by Pulse Laser Deposition
Young Jin Choi,Cheon Lee
Transactions on Electrical and Electronic Materials , 2012,
Abstract: In this study, ZnO films have been grown on PES (polyethersulfone) of flexible polymer substrate by PLD (pulsed laserdeposition) and characterized for crystalline and optical properties. Growing conditions were changed with substratetemperatures ranging from 50 to 200℃ and laser power density ranging from 0.2 to 0.4 J/cm2. When ZnO thin filmsare deposited at low temperature with a small laser power density, the (002) peaks of XRD to signify the crystal qualityof ZnO thin films appear to be very weak and the (101) peaks to signify the chemical composition of oxygen andzinc are strong. The (002) peaks increase with the substrate temperature and laser power density because the energyneeded for the supply of the combination regarding zinc and oxygen has increased. In this study, the best conditionfor growing ZnO thin film on PES is at a substrate temperature of 200℃ and with a laser density of 0.3 J/cm2. Thecharacteristics of PL were measured by UV and green luminescence.
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