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Search Results: 1 - 10 of 1576 matches for " Har Narayan Upadhyay "
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Enhanced Test Data Compression of Conflict Bit Using Clustering Technique
S. Saravanan,Har Narayan Upadhyay
Research Journal of Applied Sciences, Engineering and Technology , 2012,
Abstract: The aim of this study is to implement enhanced test data compression of conflict bit using clustering technique. Huge test patterns, larger power consumption and more accessing time are the various challenges encountered by present System on Chip (SOC) design. Various compression techniques have been developed to minimize the huge test patterns by reducing the size of the data which saves space and transmission time. Test quality of the test pattern can be improved by test data compression. By finding the proper conflict bit (‘U’) the proposed algorithm generates test patterns having high reduction in test compression. Small numbers of test patterns are generated using clustering technique. With proper test pattern clustering it is possible to achieve high level of compression. Validation of the proposed method is found by experimental results on ISCAS’89 and shows that compression ratio is achieved by 79% with less conflict test pattern.
Effective LFSR Reseeding Technique for Achieving Reduced Test Pattern
S. Saravanan,Har Narayan Upadhyay
Research Journal of Applied Sciences, Engineering and Technology , 2012,
Abstract: Aim of this study is to focus on reducing test pattern with effective Linear Feedback Shift Register (LFSR) reseeding. Test data volume of modern devices for testing increases rapidly corresponding to the size and complexity of the Systems-on-Chip (SoC). LFSR is a good pseudorandom pattern generator, which generates all possible test vectors with the help of the tap sequence. It can achieve high fault coverage by reducing correlation between the test vectors. Reseeding is a powerful method for reducing the test data volume and storage. This study presents a new LFSR reseeding technique for efficient reduction of test pattern. A new encoding technique is proposed in this study which is used to reduce the size of the test data. Size of the test data can be reduced by LFSR clock which is inactive for several clock cycles after the input seed is given. When the clock goes to inactive state, a rotate right shift operation is done on the seed to get all the remaining possible values. After getting all the possible values for that seed a new seed is given by making the clock active. Test data volume is reduced by storing the data only when the clock is active. With in the reduced clocks, rest of all the remaining test vectors was derived. A special Control logic is used to make the clock active as well as inactive. Experimental results are targeted to ISCAS89 benchmark circuits.
Achieving Low Power Test Pattern By Efficient Compaction Method For SoC Design
S. Saravanan,Har Narayan Upadhyay
Journal of Artificial Intelligence , 2012,
Abstract: Present System-on-Chip (SoC) contains various design models and all the design components are integrated into single Integrated Chip (IC). Thus total volume of SoC test pattern is also growing in complex manner. This huge test pattern also invokes various challenges in switching power, memory space and accessing time. The problem on huge test pattern involved for scan based testing is focused in this research. Coloring algorithm is proposed to compact test pattern. Utilization of unspecified test pattern promises more compaction in coloring algorithm. This proposed method never contains any extra silicon area overhead. Due to this advantage, proposed technique is more suitable for reduction of test pattern. An experimental result produces significant reduction in above said problems and tested with ISCAS89 benchmark circuits.
Run-Length Based Efficient Compression for System-on-Chip
A. Balasubramaniyan,S. Saravanan,Har Narayan Upadhyay
Journal of Artificial Intelligence , 2013,
Abstract: Large test data volume is one of the major problems in the emerging System-on-Chip (SoC) and this can be reduced by test data compression techniques. Variable-to-variable length compression is one among the test data compression techniques. This study demonstrates a variable-to-variable length based compression technique called Run-Length based Efficient Compression. The patterns which are selected for doing compression can be partitioned into blocks having equal width. The partitioned blocks can be compared with the adjacent one and can be merged. A control code is used to denote the number of blocks merged. The proposed method can be tested by calculating the effect of compression on larger ISCAS’89 benchmark circuits.
Higher test pattern compression for scan based test vectors using weighted bit position method
S. Saravanan,R. Vijay Sai,Har Narayan Upadhyay
Journal of Engineering and Applied Sciences , 2012,
Abstract: Present System on Chip (SOC) complexity has brought new challenges in volume of test pattern, low power testing and area complexity. This also shows that implementing huge test pattern and its corresponding storage space are the major problems. Due to this large number of test patterns the data transition time is also increased. This paper considers this problem in scan based test pattern. This proposed approach is based on the compression of huge test pattern by weighted bit position. Test patterns with unspecified bits are considered for specified values and partitioned into necessary weighted value. Depending upon weighted bit position specified test bit is compressed. This in turn reduces the test pattern for scan based testing. The proposed technique tested on ISCAS89 shows significant compression achieved on scan based test pattern.
Analysis of Pull-in Behavior of Electrostatic MEMS Actuators for Optical Switching Applications
M. Maheswaran,M. Nambirajan,Uppari Chaitanya Chandra Yadav,Har Narayan Upadhyay
Journal of Applied Sciences , 2012,
Abstract: Micro Electromechanical Systems (MEMS) actuators experience pull-in instability in their actuation range. MEMS actuating elements are thin parallel plate capacitor electrodes separated with air gap. The electrodes are fabricated from silicon as substrate layer and gold /aluminum layer as functional layer for reflecting laser beam in optical switching application. When the top electrode is attracted towards bottom electrode, as it crosses one third distance of the gap between the electrodes, it undergoes pull-in/snap-down with bottom electrode. This condition severely limits the device operating range. These devices are operated either analog or digital mode for positioning of the top electrode. The plate electrodes actuated in tilting mode or bending mode and they are typically torsional structures or fixed-fixed structures. This paper provides theoretical pull-in analysis for the static behavior of a optical switch model. It is derived from analytical modeling of the parallel plate type with fixed-fixed structural end conditions. The effect of dielectric layer thickness is taken into account for predicting the pull-in voltage. During the piston mode actuation cycle, when the threshold (pull-in) voltage is reached, the switch is in the bent or ON state due to electrostatic repulsion/attraction and for the no voltage condition it is in the parallel or OFF state. The pull-in hysteresis behavior of the multilayered micro-actuator bending beam model is analyzed for the variation in thickness of dielectric material. In this paper, the critical role of different dielectric layer materials in bringing down the static pull-in voltage is discussed.
Survey and Analysis of Hardware Cryptographic and Steganographic Systems on FPGA
Sundararaman Rajagopalan,Rengarajan Amirtharajan,Har Narayan Upadhyay,John Bosco Balaguru Rayappan
Journal of Applied Sciences , 2012,
Abstract: Little brooks make great rivers-says a proverb. Information science involves not only the efforts made for gathering, acquiring or collecting the data that corresponds to the information but also contains the ways to save it, protect it and preserve it. The meaning of the proverb however stresses upon how to protect and secure information, as a small leakage will pave way for entire loss of information which should be protected. True, there have been various methods, approaches and algorithms proposed in the past and will emerge in future too in the areas of secure information transmission. Cryptography and steganography have been primary sources for information security. The birds eye view on the literature pertaining to the above mentioned two giants of information security spots a number of algorithms developed on both software as well as hardware platforms. This study does the survey from the literature on different cryptographic and image steganographic methods implemented on a reconfigurable hardware like FPGAs in the past. The analysis of various methods proposed earlier is also an important objective of this study.
Synthesis, spectral, 3D molecular modeling and antibacterial studies of dibutyltin (IV) Schiff base complexes derived from substituted isatin and amino acids  [PDF]
Har Lal Singh, Jangbhadur Singh
Natural Science (NS) , 2012, DOI: 10.4236/ns.2012.43025
Abstract: New dibutyltin(IV) complexes of Schiff base derived from 5-chloroindoline-2,3-dione, indoline- 2,3-dione with amino acids (tryptophan, alanine and valine) were synthesized and characterized by elemental analysis, IR, electronic spectra, conductance measurements, and biological activity. The analytical data showed that the Schiff base ligand acts as bidentate towards metal ions via the azomethine nitrogen and carboxylate oxygen by a stoichiometric reaction of M:L (1:2) to form metal complexes. NMR (1H, 13C and 119Sn) spectral data of the ligands and metal complex agree with proposed structures. The conductivity values between 14 - 27 ohm-1cm2mol-1 in DMF imply the presence of non-electrolyte species. 3D molecular modeling and analysis of bond lengths and bond angles have also been conducted for a representative compound, [Bu2Sn(L2)2], to substantiate the proposed structures. Antibacterial results indicate that the metal complexes are more active than the free ligands.
Dementia assistive system as a dense network
Dongsoo Har
Computer Science , 2015,
Abstract: As elderly population increases, portion of dementia patients becomes larger. Thus social cost of caring dementia patients has been a major concern to many nations. This article introduces a dementia assistive system operated by various sensors and devices installed in body area and activity area of patients. Since this system is served based on a network which includes a number of nodes, it requires techniques to reduce the network performance degradation caused by densely composed sensors and devices. This article introduces existing protocols for communications of sensors and devices at both low rate and high rate transmission.
Prediction of Effective Elastic Modulus of Biphasic Composite Materials  [PDF]
Anupama Upadhyay, Ramvir Singh
Modern Mechanical Engineering (MME) , 2012, DOI: 10.4236/mme.2012.21002
Abstract: Two semi-empirical approaches for prediction of elastic modulus of biphasic composites have been proposed. Developed relations are for pore free matrix and pore free filler and found to depend on nonlinear contribution of volume fraction of constituents as well as ratio of elastic properties of individual phases. These relations are applied for the calculation of effective elastic modulus mainly for Al2O3-NiAl, SiC-Al, Alumina-Zirconia, Al-Al2O3, W-glass and Flax-Resin composite materials. Theoretical predictions using developed relations are compared with experimental data. It is found that the predicted values of effective elastic modulus using modified relations are quite close to the experimental results.
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