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Search Results: 1 - 10 of 18514 matches for " Han Zhengsheng "
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Influence of Floating Body Effect on Radiation Hardness of PD SOI nMOSFETs
Zhao Hongchen,Hai Chaohe,Han Zhengsheng,Qian He,
Zhao Hongchen
,Hai Chaohe,Han Zhengsheng,and Qian He

半导体学报 , 2005,
Abstract: H-gate and closed-gate PD SOI nMOSFETs are fabricated on SIMOX substrate,and the influence of floating body effect on the radiation hardness is studied.All the subthreshold characteristics of the devices do not change much after radiation of the total dose of 106rad(Si).The back gate threshold voltage shift of closed-gate is about 33% less than that of H-gate device.The reason should be that the body potential of the closed-gate device is raised due to impact ionization,and an electric field is produced across the BOX.The floating body effect can improve the radiation hardness of the back gate transistor.
Design and Fabrication of a High-Voltage nMOS Device
Li Hua,Song Limei,Du Huan,Han Zhengsheng,
Li Hu
,Song Limei,Du Huan,and Han Zhengsheng

半导体学报 , 2005,
Abstract: High-voltage nMOS devices are fabricated successfully and the key technology parameters of the process are optimized by TCAD software.Experiment results show that the device’s breakdown voltage is 114V,the threshold voltage and maximum driven ability are 1.02V and 7.5mA(W/L=50),respectively.Experimental results and simulation ones are compared carefully and a way to improve the breakdown performance is proposed.
Transconductance bimodal effect of PDSOI submicron H-gate MOSFETs
H型栅结构的亚微米PDSOI MOS器件的跨导双峰效应研究

Mei Bo,Bi Jinshun,Bu Jianhui,Han Zhengsheng,
Mei Bo
,Bi Jinshun,Bu Jianhui,Han Zhengsheng

半导体学报 , 2013,
Abstract: 一种导致器件性能降低的跨导双峰效应在窄沟道H型栅的 PDSOI PMOS器件中被观察到。本文基于制造工艺和相关器件的电学性能分析,研究了这种跨导双峰效应。结果表明,跨导双峰现象的产生是因为用于体引出的N 区域的施主杂质向P 多晶硅栅的扩散导致了多晶硅栅和衬底之间的功函数差的改变,从而使器件宽度方向上的阈值电压产生了差异,这相当于有两个寄生MOS管同主MOS管在器件宽度方向上并联。后续进行过版图优化的器件证明,只要使N 注入远离P 多晶硅0.2微米以上即可有效避免跨导双峰现象。
Investigations of Key Technologies for 100V HVCMOS Process
Song Limei,Li Hu,Du Huan,Xia Yang,Han Zhengsheng,Hai Chaohe,
Song Limei
,Li Hu,Du Huan,Xia Yang,Han Zhengsheng,Hai Chaohe

半导体学报 , 2006,
Abstract: A novel dual gate oxide (DGO) process is proposed to improve the performance of high voltage CMOS (HVCMOS) devices and the compatibility between thick gate oxide devices and thin gate oxide devices.An extra sidewall is added in this DGO process to round off the step formed after etching the thick gate oxide and poly-silicon.The breakdown voltages of high voltage nMOS (HVnMOS) and high voltage pMOS (HVpMOS) are 168 and -158V,respectively.Excellent performances are realized for both HVnMOS and HVpMOS devices.Experimental results demonstrate that the HVCMOS devices work safely at an operation voltage of 100V.
A Novel Local-Dielectric-Thickening Technique for Performance Improvements of Spiral Inductors on Si Substrates
Yang Rong,Li Junfeng,Zhao Yuyin,Chai Shumin,Han Zhengsheng,Qian He,
Yang
,Rong,Li,Junfeng,Zhao,Yuyin,Chai,Shumin,Han,Zhengsheng,an,Qian,He

半导体学报 , 2005,
Abstract: A novel local-dielectric-thickening technique i s presented for performance improvements of Si-based spiral inductors.This technique employs the processes of deposition,photolithography,and wet-etching,to locally thicken the oxide layer under the inductor,which can decrease the substrate loss and improve the inductor performance.Both the structures and processes are compact,economical,and compatible with CMOS processing.Several square spiral inductors with different inductances are fabricated,and the quality factors and the self-resonant frequencies both increase clearly with this proposed technique:for the 10nH,5nH,and 2nH inductors,the peak quality factors are effectively improved by 46.7%,49.7%,and 68.6%,respectively;however,the improvement percents of the self-resonant frequencies are more significant,which are 92.1%,91.0%,and no less than 68.1% respectively.
Investigation of the polysilicon p--i--n diode and diode string as a process compatible and portable ESD protection device
多晶PIN二极管及二极管串作良好工艺兼容并可移植ESD保护器件的研究

Jiang Yibo,Du Huan,Han Zhengsheng,
姜一波
,杜寰,韩郑生

半导体学报 , 2012,
Abstract: The polysilicon p-i-n diode displayed noticeable process-compatibility and portability in advance technologies as ESD protection device. The paper presented reverse breakdown, current leakage and capacitance characteristics for the fabricated polysilicon p-i-n diode. To evaluate ESD robustness forward and reverse TLP I-V characteristics were measured also. Besides polysilicon p-i-n diode string was investigated to further reduce capacitance and fulfill the requirements of tunable cut-in or reverse breakdown voltage. To explain the effects of device parameter, analysis and discussion about the inherent properties of polysilicon p-i-n diode were processed finally.
Model Parameters Extraction of a BSIM SOI Model Based on the Genetic Algorithm
基于遗传算法的BSIM SOI模型参数提取

Li Ruizhen,Han Zhengsheng,
李瑞贞
,韩郑生

半导体学报 , 2005,
Abstract: 提出了一种提取BSIM SOI模型参数的新方法,该方法基于遗传算法和局部优化法的结合,同时具有全局优化和局部优化的优点,提取的参数物理意义明确,并且容易得到全局最优解.该方法计算简单,不需要对模型进行深入了解和丰富的参数提取经验,易于推广使用.对用该方法得到的SOI模型进行了模拟,并将模拟结果与1.2μm CMOS/SOI测试结果进行对比,二者吻合很好,SOI器件特有的kink效应也得到了很好的拟合.
A novel SOI-DTMOS structure from circuit performance considerations
从电路特性方面考虑而提出的SOI-DTMOS新结构

Song Wenbin,Bi Jinshun,Han Zhengsheng,
宋文斌
,毕津顺,韩郑生

半导体学报 , 2009,
Abstract: The performance of a partially depleted silicon-on-insulator (PDSOI) dynamic threshold MOSFET (DTMOS) is degraded by the large body capacitance and body resistance. Increasing silicon film thickness can reduce the body resistance greatly, but the body capacitance also increases significantly at the same time. To solve this problem, a novel SOI DTMOSFET structure (drain/source-on-local-insulator structure) is proposed. From ISE simulation, the improvement in delay, obtained by optimizing p-n junction depth and silicon film thickness, is very significant. At the same time, we find that the drive current increases significantly as the thickness of the silicon film increases. Furthermore, only one additional mask is needed to form the local SIMOX, and other fabrication processes are fully compatible with conventional CMOS/SOI technology.
A High Performance 0.18μm RF nMOSFET with 53GHz Cutoff Frequency
Yang Rong,Li Junfeng,Xu Qiuxi,Hai Chaohe,Han Zhengsheng,Qian He
半导体学报 , 2006,
Abstract: 阐述了0.18μm射频nMOSFET的制造和性能. 器件采用氮化栅氧化层/多晶栅结构、轻掺杂源漏浅延伸结、倒退的沟道掺杂分布和叉指栅结构. 除0.18μm的栅线条采用电子束直写技术外,其他结构均通过常规的半导体制造设备实现. 按照简洁的工艺流程制备了器件,获得了优良的直流和射频性能:阈值电压0.52V,亚阈值斜率80mV/dec,漏致势垒降低因子69mV/V,截止电流0.5nA/μm,饱和驱动电流458μA/μm,饱和跨导212μS/μm (6nm氧化层,3V驱动电压)及截止频率53GHz.
Design of a High Precision Array Pulse Sensor in TCM
中医用高精度阵列脉搏传感器的设计

Huai Yongjin,Han Zhengsheng,
淮永进
,韩郑生

半导体学报 , 2008,
Abstract: We designed a high-precision array pulse sensor for TCM (traditional Chinese medicine) that can directly transform pulse-pressure signal into electric current signal and is compatible with CMOS technology.We adopted a sacrifice-layer craft for the transistor gate.During testing,we found that the precision of the capacitor for the array sensor is 0.5fF/hPa when the pressure was changing within the range of 1.5kPa to 9.5kPa.More importantly,the output-current and the pressure of the sensor have a good linearity and exponential characteristics.According to the data from the experiment,we conclude that the characteristic of the response-current is related to the area of the MOS gate.
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