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Search Results: 1 - 10 of 1304 matches for " Habib Mehrez "
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Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA
Emna Amouri,Habib Mehrez,Zied Marrakchi
International Journal of Reconfigurable Computing , 2013, DOI: 10.1155/2013/802436
Abstract: The wave dynamic differential logic (WDDL) has been identified as a promising countermeasure to increase the robustness of cryptographic devices against differential power attacks (DPA). However, to guarantee the effectiveness of WDDL technique, the routing in both the direct and complementary paths must be balanced. This paper tackles the problem of unbalance of dual-rail signals in WDDL design. We describe placement techniques suitable for tree-based and mesh-based FPGAs and quantify the gain they confer. Then, we introduce a timing-balance-driven routing algorithm which is architecture independent. Our placement and routing techniques proved to be very promising. In fact, they achieve a gain of 95%, 93%, and 85% in delay balance in tree-based, simple mesh, and cluster-based mesh architectures, respectively. To reduce further the switch and delay unbalance in Mesh architecture, we propose a differential pair routing algorithm that is specific to cluster-based mesh architecture. It achieves perfectly balanced routed signals in terms of wire length and switch number. 1. Introduction FPGAs are an attractive platform for cryptographic applications due to their low cost compared to full custom ASIC design and their short time to market period. In addition, their reprogrammability allows upgrading easily the cryptographic algorithm. However, unprotected hardware implementations are vulnerable to side channel attacks (SCA). It has been shown that differential power analysis (DPA) attack [1] is very powerful. DPA is capable of revealing the secret key by measuring power consumption leaked by a cryptographic device. During the last years, many countermeasures have been proposed to protect cryptographic devices against SCA. They fall into two main categories: the masking logic and the hiding logic. The principle of masking logic is to randomize the power consumption by using a random mask and thus decorrelate the intermediate data from the circuit power consumption. This technique was introduced first at algorithmic level [2] and then at gate level [3]. It has been shown that this technique can be broken by attacks based on probability density function (PDF) [4] or glitches [5]. To overcome glitch problem, masked dual rail precharge logic (MDPL) [6] has been proposed. It merges masking with dual rail dynamic logic. However, MDPL shows a high area overhead [7]. On the other side, the principle of hiding logic consists in consuming the same amount of power consumption regardless of data inputs. This is achieved by using differential logic (signals are encoded as
FPGA Interconnect Topologies Exploration
Zied Marrakchi,Hayder Mrabet,Umer Farooq,Habib Mehrez
International Journal of Reconfigurable Computing , 2009, DOI: 10.1155/2009/259837
Abstract: This paper presents an improved interconnect network for Tree-based FPGA architecture that unifies two unidirectional programmable networks. New tools are developed to place and route the largest benchmark circuits, where different optimization techniques are used to get an optimized architecture. The effect of variation in LUT and cluster size on the area, performance, and power of the Tree-based architecture is analyzed. Experimental results show that an architecture with LUT size 4 and arity size 4 is the most efficient in terms of area and static power dissipation, whereas the architectures with higher LUT and cluster size are efficient in terms of performance. We also show that unifying a Mesh with this Tree topology leads to an architecture which has good layout scalability and better interconnect efficiency compared to VPR-style Mesh.
Exploration of Heterogeneous FPGA Architectures
Umer Farooq,Husain Parvez,Habib Mehrez,Zied Marrakchi
International Journal of Reconfigurable Computing , 2011, DOI: 10.1155/2011/121404
Abstract: Mesh-based heterogeneous FPGAs are commonly used in industry and academia due to their area, speed, and power benefits over their homogeneous counterparts. These FPGAs contain a mixture of logic blocks and hard blocks where hard blocks are arranged in fixed columns as they offer an easy and compact layout. However, the placement of hard-blocks in fixed columns can potentially lead to underutilization of logic and routing resources and this problem is further aggravated with increase in the types of hard-blocks. This work explores and compares different floor-planning techniques of mesh-based FPGA to determine their effect on the area, performance, and power of the architecture. A tree-based architecture is also presented; unlike mesh-based architecture, the floor-planning of heterogeneous tree-based architecture does not affect its routing requirements due to its hierarchical structure. Both mesh and tree-based architectures are evaluated for three sets of benchmark circuits. Experimental results show that a more flexible floor-planning in mesh-based FPGA gives better results as compared to the column-based floor-planning. Also it is shown that compared to different floor-plannings of mesh-based FPGA, tree-based architecture gives better area, performance, and power results. 1. Introduction During recent past, embedded hard blocks (HBs) in FPGAs (i.e., heterogenous FPGAs) have become increasingly popular due to their ability to implement complex applications more efficiently as compared to homogeneous FPGAs. The work in [1] shows that the use of embedded memory in FPGA improves its density and performance. Beauchamp et al. [2] have incorporated floating point multiply-add units in the FPGA and have reported significant area and speed improvements over homogeneous FPGAs. Ho et al. [3] have proposed a virtual embedded block (VEB) methodology that predicts the effects of embedded blocks in commercial FPGA devices, and they have shown that the use of embedded blocks causes an improvement in area and speed efficiencies. Also Govindu et al. [4] and Underwood and Hemmert [5] suggest the use of embedded blocks in FPGAs for better performance regarding complex scientific applications. The work in [6] shows that the use of HBs in FPGAs reduces the gap between ASIC and FPGA in terms of area, speed and power consumption. Some of the commercial FPGA vendors like Xilinx [7] and Altera [8] are also using HBs (e.g., multipliers, memories, and DSP blocks). Almost all the work cited above considers mesh-based (island-style) FPGAs as the reference architecture where HBs
Frequency Optimization Objective during System Prototyping on Multi-FPGA Platform
Mariem Turki,Zied Marrakchi,Habib Mehrez,Mohamed Abid
International Journal of Reconfigurable Computing , 2013, DOI: 10.1155/2013/853510
Abstract: Multi-FPGA hardware prototyping is becoming increasingly important in the system on chip design cycle. However, after partitioning the design on the multi-FPGA platform, the number of inter-FPGA signals is greater than the number of physical connections available on the prototyping board. Therefore, these signals should be time-multiplexed which lowers the system frequency. The way in which the design is partitioned affects the number of inter-FPGA signals. In this work, we propose a set of constraints to be taken into account during the partitioning task. Then, the resulting inter-FPGA signals are routed with an iterative routing algorithm in order to obtain the best multiplexing ratio. Indeed, signals are grouped and then routed using the intra-FPGA routing algorithm: Pathfinder. This algorithm is adapted to deal with the inter-FPGA routing problem. Many scenarios are proposed to obtain the most optimized results in terms of prototyping system frequency. Using this technique, the system frequency is improved by an average of 12.8% compared to constructive routing algorithm. 1. Introduction With the ever increasing complexity of system on chip circuits, the software and hardware developers can no longer wait for the fabrication phase to test their designs [1]. Currently, it is estimated that 60 to 80 percent of an ASIC design is spent in performing verification [2]. FPGA-based prototyping is an important step in the creation of the final product and it is the key to the success of marketing in time. The key advantage of FPGA-based prototyping is the ability to run at high speed (sometimes at almost real-time speed) a cycle-accurate, bit-accurate model of the SoC [3]. The availability of automatic FPGA mapping tools has streamlined the design conversion process, making the path from ASIC design to FPGA implementation more straightforward. When the logic capacity of a single FPGA is less than the size of the design under test, a multi-FPGA platform is used to map the entire design. Because the silicon area overhead of FPGA versus ASIC technology has been measured to be about 40x [4], FPGA programming technology requires that an ASIC logic design be partitioned across multiple FPGA devices to achieve the necessary device logic capacity. The number of FPGAs depends on the size of the prototyping system, ranging from a few [5] up to 60 FPGAs [6]. In order to map the design into a multi-FPGA board, a partitioning tool decomposes the design into pieces that will fit within the logic resources of individual FPGA devices. Partitioning is often performed to
EPIDEMIOLOGY OF ACTIVATED PROTEIN C RESISTANCE AND FACTOR V LEIDEN MUTATION IN THE MEDITERRANEAN REGION
Mehrez Mehrez M. Jadaon
Mediterranean Journal of Hematology and Infectious Diseases , 2011, DOI: 10.4084/mjhid.2011.
Abstract:
Extension of Huygens type inequalities for Bessel and modified Bessel Functions
Khaled Mehrez
Mathematics , 2015,
Abstract: In this paper, new sharpened Huygens type inequalities involving Bessel and modified Bessel functions of the first kinds are established
Some new refined Hardy type integral inequalities
Khaled Mehrez
Mathematics , 2015,
Abstract: In this paper, by using Jensen's inequality and Chebyshev integral inequality, some generalizations and new refined Hardy type integral inequalities are obtained. In addition, the corresponding reverse relation are also proved.
Logarithmically completely monotontic functions related the $q-$gamma and the $q-$digamma functions with applications
Khaled Mehrez
Mathematics , 2015,
Abstract: In this paper we present several new classes of logarithmically completely monotonic functions. Our functions have in common that they are defined in terms of the $q-$gamma and $q-$digamma functions. As an applications of this results, some inequalities for the $q-$gamma and the $q-$digamma functions are established. Some of the given results generalized theorems due to Alzer and Berg and C.-P. Chen and F. Qi.
Turán Type Inequalities for The $q$-exponential functions
Khaled Mehrez
Mathematics , 2015,
Abstract: In this paper our aim is to deduce some sharp Tur\'an type inequalities for the remainder $q-$exponential functions. Our results are shown to be a generalization of results which were obtained by Alzer \cite{al}.
Supply Chain Management (SCM): Its Future Implications  [PDF]
Mamun Habib
Open Journal of Social Sciences (JSS) , 2014, DOI: 10.4236/jss.2014.29040
Abstract:

This keynote paper represents theory of Supply Chain Management (SCM) and its future implications as well as demonstrates chronological prospective of SCM in terms of time frame in different areas of manufacturing and service industries. SCM has been widely researched in numerous application domains during the last decade. Despite the popularity of SCM research and applications, considerable confusion remains as to its meaning. There are several attempts made by researchers and practitioners to appropriately define SCM. Amidst fierce competition in all industries, SCM has gradually been embraced as a proven managerial approach to achieving sustainable profits and growth. Finally, this study demonstrates Educational Supply Chain Management, as the application of SCM in the service industry, which would unlock other applications of SCM in different arenas. Integrated Tertiary Educational Supply Chain Management (ITESCM) model would be verified through Structural Equation Modeling (SEM) Techniques that would describe in this paper. The ITESCM model furnishes stakeholders of the supply chain with appropriate strategies to review and appraise their performance toward fulfillment of ultimate goals, i.e. producing high-ca- liber graduates and high-impact research outcomes, which represent two main contributions, for the betterment of the society.

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