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Search Results: 1 - 10 of 20525 matches for " Fu-Chien Chiu "
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Surface State Capture Cross-Section at the Interface between Silicon and Hafnium Oxide
Fu-Chien Chiu
Advances in Materials Science and Engineering , 2013, DOI: 10.1155/2013/950439
Abstract: The interfacial properties between silicon and hafnium oxide (HfO2) are explored by the gated-diode method and the subthreshold measurement. The density of interface-trapped charges, the current induced by surface defect centers, the surface recombination velocity, and the surface state capture cross-section are obtained in this work. Among the interfacial properties, the surface state capture cross-section is approximately constant even if the postdeposition annealing condition is changed. This effective capture cross-section of surface states is about 2.4 × 10?15?cm2, which may be an inherent nature in the HfO2/Si interface. 1. Introduction Hafnium oxide (HfO2) has emerged recently as an essential dielectric material in the semiconductor industry, currently being used in logic gate stacks [1] and considered a promising candidate for resistance switching memory devices [2, 3] as well as surface passivation of advanced Si solar cells [4, 5]. Therefore, the determination of surface state capture cross-section at the interface between silicon and hafnium oxide is of great importance for the semiconductor industry, the photovoltaic industry, and the scientific community. The known characteristics of HfO2 thin films include a large band gap (~6?eV) [6], a relatively high dielectric constant (>20) [7], an acceptable breakdown strength (>4?MV/cm) [7], excellent thermodynamic stability [8], and an effective mass of carrier transportation [9]. In this work, the interface characteristics of the interface-trapped charge density ( ), the interface-trapped charge density per area and energy ( ), the effective capture cross-section ( ) of surface states, the surface recombination velocity ( ), and the minority carrier lifetime ( ) are identified. The typically electrical measurements of current-voltage ( ) and capacitance-voltage ( ) characteristics were performed on the Al/HfO2/p-Si metal-oxide-semiconductor (MOS) capacitors and metal-oxide-semiconductor field-effect transistors (MOSFETs). Both gated-diode method [10, 11] and subthreshold measurement [12] were applied to evaluate the capture cross-section of interface states for the HfO2-gated MOSFETs. The gated-diode method is a simple way to accurately identify the interfacial characteristics using only a sweeping dc gate voltage, which was introduced in 1966 by Grove and Fitzgerald [10] to determine the surface-state density in MOS structures. According to the gated-diode measurements, the surface recombination velocity and the minority carrier lifetime ( ) in the field-induced depletion region were extracted.
Resistance Switching Characteristics in ZnO-Based Nonvolatile Memory Devices
Fu-Chien Chiu
Advances in Materials Science and Engineering , 2013, DOI: 10.1155/2013/362053
Abstract: Bipolar resistance switching characteristics are demonstrated in Pt/ZnO/Pt nonvolatile memory devices. A negative differential resistance or snapback characteristic can be observed when the memory device switches from a high resistance state to a low resistance state due to the formation of filamentary conducting path. The dependence of pulse width and temperature on set/reset voltages was examined in this work. The exponentially decreasing trend of set/reset voltage with increasing pulse width is observed except when pulse width is larger than 1?s. Hence, to switch the ZnO memory devices, a minimum set/reset voltage is required. The set voltage decreases linearly with the temperature whereas the reset voltage is nearly temperature-independent. In addition, the ac cycling endurance can be over 106 switching cycles, whereas, the dependence of HRS/LRS resistance distribution indicates that a significant memory window closure may take place after about 102? dc switching cycles. 1. Introduction Developments of next generation nonvolatile memory (NVM) devices are required because the physical limitations of traditional Flash memory devices are approaching. In recent years, the resistance random access memory (RRAM) device has attracted a great deal of attention for the next generation NVM applications [1]. Since the RRAM technology is well compatible with the complimentary metal oxide semiconductor (CMOS) process [2], the scaling of RRAM devices may keep on in terms of the low power operation. This benefit will bring a strong cost-competitiveness to RRAM. In addition, the advantages of RRAM include small cell size, simple cell structure, high switching speed, high operation durability, multi state switching, and three-dimensional architecture [1–5]. The resistance switching behavior has been reported for a variety of materials such as perovskite-type oxides [1, 3], binary metal oxides [2–4], solid-state electrolytes [4], organic compounds [6], and amorphous Si [7]. In these RRAM materials being studied, binary metal oxides are most potential due to their simple constituents, good compatibility with CMOS processes, and resistive nature to thermal/chemical damages [2, 4, 8]. In this work, Pt/ZnO/Pt capacitors were fabricated and investigated for the NVM applications. The dependence of pulse width and temperature on set/reset voltages was examined. Experimental results show that a minimum set/reset voltage is required to switch the ZnO memory devices. The exponential decreasing trend of set/reset voltage with increasing pulse width is observed except when pulse
A Substrate-and-Gate Triggering NMOS Device for High ESD Reliability in Deep Submicrometer Technology
Chih-Yao Huang,Fu-Chien Chiu
Advances in Materials Science and Engineering , 2013, DOI: 10.1155/2013/905686
Abstract: A substrate-and-gate triggering scheme which utilizes dynamic threshold principle is proposed for an ESD NMOS structure. This scheme enhances the device reliability performance in terms of higher second breakdown current and both reduced holding voltage/triggering voltage as well as elimination of gate over driven effect. The simple resistance and RC substrate-and-gate triggering NMOS structure with various resistance/capacitance values totally exhibit superior ESD reliability than the gate-grounded NMOS (GGNMOS) devices by 18~29%. The substrate-and-gate triggering scheme in combination with special substrate pickup styles also shows excellent enhancement when compared with the GGNMOS cases of the same pickup styles. The substrate-and-gate triggering NMOS with butting substrate pickup style is better than the general butting case by 28~30%, whereas the substrate-and-gate triggering NMOS with inserted substrate pickup style is 3.5 times superior to the general inserted case. 1. Introduction Electrostatic discharge (ESD) issue has become a more serious device reliability problem in semiconductor components and systems. An NMOSFET has been the most popular ESD protection candidate for a long time. Since the shrinking of device size advances continually, the ESD capability of the NMOS device encounters more challenges [1–7]. A gate-grounded NMOS (GGNMOS) can no longer satisfy the ESD protection mission easily. ESD NMOS protection devices usually need the large width size to deal with ESD events. This results in multifinger layout style which is commonly used in practical IC I/O area. But it also has a critical drawback which is not favorable for the ESD protection requirement. The conduction current is usually unevenly distributed along the width direction of the multifingers. Gate-coupling technique using the property that increases the gate bias can reduce the first trigger point of the NMOS device and enable uniform ESD current distribution [4, 8, 9]. Although gate-coupling technique can improve the ESD capability, it still has gate overdriven effect if the gate voltage coupled is much larger than its threshold voltage, and this leads to serious ESD degradation. Furthermore, inserted or butting substrate pickups in the source diffusion region of the ESD NMOS device in deep submicrometer technology also degraded ESD reliability seriously. Such layout style has been strictly prohibited in practical ESD design applications by the technology design rules. Therefore, in this work, a new substrate-and-gate triggering (SGT) structure that utilizes dynamic
Charge-Trapping Devices Using Multilayered Dielectrics for Nonvolatile Memory Applications
Wen-Chieh Shih,Chih-Hao Cheng,Joseph Ya-min Lee,Fu-Chien Chiu
Advances in Materials Science and Engineering , 2013, DOI: 10.1155/2013/548329
Abstract: Charge-trapping devices using multilayered dielectrics were studied for nonvolatile memory applications. The device structure is Al/Y2O3/Ta2O5/SiO2/Si (MYTOS). The MYTOS field effect transistors were fabricated using Ta2O5 as the charge storage layer and Y2O3 as the blocking layer. The electrical characteristics of memory window, program/erase characteristics, and data retention were examined. The memory window is about 1.6?V. Using a pulse voltage of 6?V, a threshold voltage shift of ~1?V can be achieved within 10?ns. The MYTOS transistors can retain a memory window of 0.81?V for 10 years. 1. Introduction One of the most attractive candidates for nonvolatile memory applications is the charge-trapping device in which multilayered dielectrics are used. The semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory is typical of the charge-trapping devices. The advantages of SONOS-type charge-trapping devices include smaller cell size, lower programming voltage, and better cycling endurance compared with the floating-gate devices. By reducing the tunneling oxide thickness in the SONOS-type devices, faster programming speed and lower operating voltage can be accomplished [1–4]. However, the issues of poor retention time and low erase speed still remain in the SONOS-type memory devices. To improve the retention time of SONOS devices, several researches have been reported. Hsu et al. indicated that HfO2 can replace Si3 N4 and obtain a higher conduction band offset for better retention [5]. Reports showed that the retention of memory devices can be improved using a chemical-vapor-deposited blocking oxide [6] or implementing a high-temperature deuterium annealing [7]. Additionally, using a high-k dielectric as the blocking oxide, the program/erase speed and retention characteristic can be improved [8, 9]. In the study using Si3 N4, HfO2, and HfAlO as the charge storage layer, Tan et al. showed that larger band offset can improve the program speed and reduce the overerase phenomenon [10]. Furthermore, using the structures of TaN/HfO2/T2 O5/HfO2/Si (MHTHS) and TaN/Al2O3/Ta2O5/HfO2/Si (MATHS) both program speed and retention time can be improved as compared to the traditional SONOS devices [11, 12]. In this work, charge-trapping devices using multilayered dielectrics were studied for nonvolatile memory applications. The structure is metal—yttrium oxide—tantalum oxide—silicon oxide—silicon (MYTOS), that is, Al/Y2O3/Ta2O5/SiO2/Si. The MYTOS devices were fabricated using Ta2O5 as the charge storage layer and Y2O3 as the blocking oxide for both high energy
The Design of Decomposed Scorm Structure With Embedded LCMS Broker.
Fu-Chien Kao,,Chih-Wei Tseng,,Wen-Yu Chang,,Chang-Yu Huang
International Journal of Computer Science & Applications , 2008,
Abstract:
The Design of Ubiquitous Learning System with Embedded Ganglia Agent
Fu-Chien Kao,Chia-Chun Hung,Ting-Hao Huang
International Journal of Computer Science Issues , 2011,
Abstract: This research proposes a context-aware computing ubiquitous learning system architecture design. The system integrates data grid, the ability to perform context-awareness computing, and embedded Ganglia Agent design, structuring an architecture that is able to perform context awareness mobile network, creating a ubiquitous learning environment. The embedded Ganglia Agent could provide context information on system network traffic, the CPU load of the content server, and hard disk capacity, and utilize the information to balance the load of back-end content server, providing a flexible expandability mechanism for the back-end content server. The framework of the proposed ubiquitous learning system that has context-awareness computing ability is consisted of 3 major parts: Learning Management System (LMS), Learning Content Management System (LCMS) and the embedded Ganglia Agent (EGA). LMS is responsible for managing the learners basic personal information and studying records, LCMS is responsible for the management and storage of back-end learning contents, and EGA is responsible for the management network traffic, CPU load and hard disk capacity. With the three, the load of the back-end content server could be balanced, offering a flexible mechanism for the expansion of the server.
The Design of Circuit-Measuring Collaborative Learning System with Embedded Broker
Fu-Chien Kao,Siang-Ru Wang,Ting-Hao Huang
International Journal of Computer Science Issues , 2010,
Abstract: Recently, the academic community has been giving much attention to Cooperative Learning System, a group learning method combined with pedagogy and social psychology. It allows group members to gain knowledge through collaborations and interactions. Nowadays, most Internet cooperative learning systems are designed to provide students mainly with a convenient online environment to study theoretical courses but rarely with an online environment to operate practical instruments. Hence, this paper designed a 3D online cooperative learning system for operating virtual instruments with circuit-measuring function. By integrating with Virtual Reality, Remote Control Parameter Transmission and embedded system techniques, this system gives learners not only a cooperative learning environment via networking to jointly operate the 3D virtual instruments (for example, multi-meters, power supplies and oscilloscopes) but also the functions of instant messages and 3D puzzles to interact with one another. Therefore, learners can effectively improve learning interests and results.
The Design of Circuit-Measuring Collaborative Learning System with Embedded Broker
Fu-Chien Kao,Siang-Ru Wang,Ting-Hao Huang
Computer Science , 2010,
Abstract: Recently, the academic community has been giving much attention to Cooperative Learning System, a group learning method combined with pedagogy and social psychology. It allows group members to gain knowledge through collaborations and interactions. Nowadays, most Internet cooperative learning systems are designed to provide students mainly with a convenient online environment to study theoretical courses but rarely with an online environment to operate practical instruments. Hence, this paper designed a 3D online cooperative learning system for operating virtual instruments with circuit-measuring function. By integrating with Virtual Reality, Remote Control Parameter Transmission and embedded system techniques, this system gives learners not only a cooperative learning environment via networking to jointly operate the 3D virtual instruments (for example, multi-meters, power supplies and oscilloscopes) but also the functions of instant messages and 3D puzzles to interact with one another. Therefore, learners can effectively improve learning interests and results.
Efficient 1H-NMR Quantitation and Investigation of N-Acetyl-D-glucosamine (GlcNAc) and N,N'-Diacetylchitobiose (GlcNAc)2 from Chitin
Fu-Chien Liu,Chung-Ren Su,Tzi-Yi Wu,Shyh-Gang Su,Huey-Lang Yang,John Han-You Lin,Tian-Shung Wu
International Journal of Molecular Sciences , 2011, DOI: 10.3390/ijms12095828
Abstract: A quantitative determination method of N-acetyl- D-glucosamine (GlcNAc) and N, N '-diacetylchitobiose (GlcNAc) 2 is proposed using a proton nuclear magnetic resonance experiment. N-acetyl groups of GlcNAc and (GlcNAc) 2 are chosen as target signals, and the deconvolution technique is used to determine the concentration of the corresponding compound. Compared to the HPLC method, 1H-NMR spectroscopy is simple and fast. The method can be used for the analysis of chitin hydrolyzed products with real-time analysis, and for quantifying the content of products using internal standards without calibration curves. This method can be used to quickly evaluate chitinase activity. The temperature dependence of 1H-NMR spectra (VT-NMR) is studied to monitor the chemical shift variation of acetyl peak. The acetyl groups of products are involved in intramolecular H-bonding with the OH group on anomeric sites. The rotation of the acetyl group is closely related to the intramolecular hydrogen bonding pattern, as suggested by the theoretical data (molecular modeling).
Results of Microendoscopic Discectomy Performed in the 26 Cases with a Minimum 3 Years Follow-up
Shih-Sheng Chang,Tsai-Sheng Fu,Yen-Chiu Liang,Chi-Chien Niu
Chang Gung Medical Journal , 2009,
Abstract: Background: Microendoscopic discectomy (MED) is less invasive than conventional opendiscectomy, but the long-term benefits of this technique are still debated.Controversy also remains regarding the surgical indications, patient selection,effectiveness, learning curve and complications.Methods: From Dec 2001 to Dec 2003, 26 patients with lumbar herniated disc diseasereceived MED. The surgical indications included the following: (1) unilateral,single level lumbar disc herniation; (2) signs and symptoms compatiblewith the involved nerve root; (3) failure of conservative treatment. Thesecases were the initial MEDs performed by one of our senior authors (TS FU).Clinical symptoms and outcomes were assessed using the JapaneseOrthopaedic Association Back Scores.Results: Treatment in two cases was changed to open discectomy because of irreparabledural tears during surgery. For the remaining 24 cases, the average intraoperativeblood loss was 55.8 mL. The average operation length was 136.8minutes and the average post-surgical hospital stay was 2.4 days. At 12weeks after the operation, 22 achieved excellent or good results. The satisfactoryrate was 91.7%. On final follow-up, 21 patients had excellent or goodresults. The satisfactory rate was 87.5%. Complications included twoirreparable dural tears, two superficial wound infections and onepseudomenigocele.Conclusions: Our data indicate that MED is an effective procedure for lumbar disc herniation.The result is satisfactory under adequate surgical indications and patientselection. Despite the low complication rate, dural tears still remain a concernduring the learning stage.
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