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Search Results: 1 - 10 of 176670 matches for " Bishnu Prasad De "
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New Delay and Power Analysis for a CMOS Inverter Driving RLC Interconnect
Sohini Mondal,Bishnu Prasad De
International Journal of Engineering and Advanced Technology , 2013,
Abstract: In this era, the on-chip interconnect delay is significantly more dominating than the gate delay. Several approaches have been proposed to capture the interconnect delay accurately and efficiently. Here delay and power analysis for a CMOS inverter driving a resistive-inductive-capacitive load is presented. A closed form delay and power model of a CMOS inverter driving a resistive-inductive-capacitive load is discussed. The model is derived from Sakurai’s alpha-power law and exhibits good accuracy. The model can be used for the design and analysis of the CMOS inverters that drive a large interconnect RLC load when considering both speed and power. Closed form expressions are also presented for the propagation delay and transition time which exhibit less than 15% error compared to the SPICE for a wide range of RLC loads. Explicit methods are also provided for modeling the short-circuit power dissipation of a CMOS inverter driving a RLC line. The average error is within 22% compared to SPICE for most practical loads.
Performance Analysis of High Speed Low Power Carry Look-Ahead Adder Using Different Logic Styles
Jagannath Samanta,Mousam Halder,Bishnu Prasad De
International Journal of Soft Computing & Engineering , 2013,
Abstract: A carry look-ahead adder improves speed byreducing the amount of time required to resolve carry bits. It iswidely used in any electronic computational devices. In this papera 4 bit & 8 bit CLA has been implemented using different staticand dynamic logic styles such as Standard CMOS, DCVS PseudoNMOS, PTL & Domino logic style. The performance of the CLAhas been measured by comparing the results in terms ofpropagation delay, power dissipation and their Power DelayProduct. The simulation is done with the help of Tanner EDA toolconsidering the different feature sizes of 150nm, 200nm &250nm. Result analyses are also carried out for intrinsic andextrinsic load capacitances. This work will helpful for any circuitdesigner to build any system.
Design and Implementation of Low-Power High-Performance Carry Skip Adder
Santanu Maity,Bishnu Prasad De,Aditya Kr. Singh
International Journal of Engineering and Advanced Technology , 2012,
Abstract: The most timing critical part of logic design usually contains one or more arithmetic operations, in which addition is commonly involved. In VLSI applications, area, delay and power are the important factors which must be taken into account in the design of a fast adder. The carry-skip adder reduces the time needed to propagate the carry by skipping over groups of consecutive adder stages, is known to be comparable in speed to the carry look-ahead technique while it uses less logic area and less power. In this paper, a design of 8-bit Carry Skip Adder by various existing logic styles are to be compared quantitatively and qualitatively by performing detailed transistor-level simulation using T-Spice v13.0.
Comparative study for delay & power dissipation of CMOS Inverter in UDSM range
Jagannath Samanta,Bishnu Prasad De,Banibrata Bag,Raj Kumar Maity
International Journal of Soft Computing & Engineering , 2012,
Abstract: Delay and power are two major issues indesign and synthesis of VLSI circuits which dependson different design parameters. In this paper, therelative study of propagation delay and powerconsumption of UDSM CMOS inverter is foundconsidering the channel length below 100nm. Thesimulation results are taken for different technology(32nm, 45nm, 65nm and 90nm) with the help of Tanner(T-spice) simulation tool. The values of modelparameters are used from current Berkeley PredictiveTechnology Model (PTM). Also the results areanalyzed by varying load capacitance, supply voltage& transistor widths.
State Estimation and Voltage Stability Monitoring Using ILP PMU Placement
Aditya Kumar Singh,Bishnu Prasad De,Santanu Maity
International Journal of Soft Computing & Engineering , 2012,
Abstract: Low power VLSI circuits have become important criteria for designing the energy efficient electronic designs for high performance and portable devices .The multipliers are the main key structure for designing an energy efficient processor where a multiplier design decides the digital signal processors efficiency. In this paper, 4*4 unsigned Array and Tree multiplier architecture is being designed by using 1-bit full adders and AND2 function following various logic styles. The full adders and AND2 function have been designed using various logic styles following a unique pattern of structure to improve their performance in various means like less transistors, low power, minimal delay, and increased power delay product. The various types of adders used in our paper are complementary MOS (CMOS) logic style, complementary pass-transistor (CPL) logic style and double-pass transistor (DPL) logic style. The main objective of our work is to calculate the average power, delay and power delay product of 4*4 bit multipliers following various logic styles at 5v supply voltage at 25c temperature with 0.15um technology and simulating them with T-spice of Tanner EDA tool. An multiplier architecture is designed using full adder, half adder structure and AND2 function and then the above said various logic style adders and AND2 function are replaced in the multiplier architecture and then their outputs are generated, such that their average power, delay, and power delay product are calculated.
Status of Critically Endangered Vultures in Dang Deukhuri Foothill Forests and West Rapti Wetlands
Bishnu Prasad Shrestha,Bishnu Prasad Devkota
The Initiation , 2011, DOI: 10.3126/init.v4i0.5533
Abstract: Vultures play a highly important ecological role through the rapid consumption of animal carcasses. Of 22 vulture species in the world, eight species are found in Nepal. The study was carried out in Dang Deukhuri valley with objectives of assessing present population status of critically endangered vultures and conservation threats to these vultures. To study population status, direct survey and repeated absolute count methods were used; population size estimated through Jacknife technique; nest occupancy determined by nest census method. Similarly, interview/household surveys were conducted to assess the present food availability and livestock condition; conservation threats to vultures. The range of absolute population size of the critically endangered vultures; Gyps bengalensis, Gyps tenuirostris and Sarcogyps calvus were found 44, 21 and 18 respectively in Dang Deukhuri valley. The major threat to vultures is diclofenac contamination of livestock carcasses and other threats are habitat destruction, disturbance & hunting, lack of awareness, food shortage, poisoning and pesticide use in the area. DOI: http://dx.doi.org/10.3126/init.v4i0.5533 The Initiation Vol.4 2011 28-34
Measuring the price of labour in agricultural economies: the shadow wage rate
Bishnu Prasad Sharma
Economic Journal of Development Issues , 2013, DOI: 10.3126/ejdi.v15i1-2.11860
Abstract: ? Labour market imperfections are one of the leading causes of economic backwardness that result in under utilization of labour, the most important input in production process. Labour markets are shallow in subsistence agricultural economies which causes problem in determining the wage rate. The household production function provides an alternative to estimating the shadow wage rate such that it reflects the opportunity cost of labour. The most important deductions of the household production function are: the marginal productivity of labour is its shadow wage rate and; at equilibrium, the marginal returns from labour are exactly equal across all activities. This paper uses data collected in 2008 in course of a leasehold forestry study from 297 households from Makwanpur district of Nepal using a multi stage sampling. This paper estimates the marginal productivity of labour in maize production, the most common form of economic activity, for male and female labour. It examines how the money wage rate and the actual wage rate may differ from the shadow wage rate reflected by marginal productivity of labour in agriculture. The findings reveal that the actual wage rate for male labour is inflated and exceeds its marginal productivity while female wage rate slightly understates its marginal productivity. The paper concludes with policy recommendation of ensuring institutional mechanisms to correct for these imperfections. ? DOI: http://dx.doi.org/10.3126/ejdi.v15i1-2.11860 Economic Journal of Development Issues Vol. 15 & 16 No. 1-2, pp. 24-35 ?
A Model for the Development of Universal Browser for Proper Utilization of Computer Resources Available in Service Cloud over Secured Environment
Bishnu Prasad Gautam,Dipesh Shrestha
Lecture Notes in Engineering and Computer Science , 2010,
Abstract:
Document Clustering Through Non-Negative Matrix Factorization: A Case Study of Hadoop for Computational Time Reduction of Large Scale Documents
Bishnu Prasad Gautam,Dipesh Shrestha
Lecture Notes in Engineering and Computer Science , 2010,
Abstract:
Effective Campus Management through Web Enabled Campus-SIA (Student Information Application)
Bishnu Prasad Gautam,Shree Krishna Shrestha
Lecture Notes in Engineering and Computer Science , 2012,
Abstract:
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