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Prevalence of unilateral hearing loss among kindergarteners aged 3-6 years in Hamadan city, 2012
Atta Heidari,Ayub Valadbeigi
Pajouhan Scientific Journal , 2012,
Abstract: Introduction: Unilateral hearing loss has devastating effects on sound localization, speech understanding in adverse listening conditions, academic achievement, behavior and learning of Hearing impaired children. Early detection and intervention with regard to the issues of unilateral hearing loss is important in young children. The main goal of this study was to determine the prevalence of unilateral hearing loss among kindergarteners aged 3-6 years in Hamadan city, 2012.Material and Methods: In this cross-sectional descriptive study, 345 subjects (185 female, 160 male) were selected through random sampling. Play Audiometry test was used to determine the hearing threshold.Results: The results indicated that from the sum of 690 ears, 30(4.3%), had unilateral hearing loss; 26 (3.8%) with conductive hearing loss, 3 (0.4%) with sensorineural hearing loss and one (0.1%) with mixed hearing loss. No significant differences were observed between paired ears, genders and different ages.Conclusion: In this study, the prevalence of unilateral hearing loss was high (4.3%), 3.8% is conductive hearing loss accruing least one during childs language learning. Given the high prevalence of unilateral hearing loss in children 3-6 years of age, and the importance of this period in speech, language and learning development, early diagnosis and intervention is essential.
Comparison of phonological awareness between children with cochlear implants and children with hearing aids
Farzad Weisi,Mohammad Rezaei,Gohar Lotfi,Ayub Valadbeigi
Pajouhan Scientific Journal , 2013,
Abstract: Introduction: Advanced phonological skills are important for the acquisition of reading skills. Children with hearing impairment have reading skills are weaker than others because of auditory inputs and due to the defect in phonological skills. The use of hearing aids and cochlear implants help to collect information on people who are hard of hearing.Material and Methods: This descriptive - analytic study was done on 12 children with cochlear implant and 12 children with hearing aids that was selected from second grades students of Tehran primary schools. Children's phonological performance was assessed by phonological subtests of Nama reading test and the data were analyzed using SPSS 16.Results: The results showed that the means of scores of children with cochlear implants in Rhyme task were significantly greater than the children with hearing aids (P=0.034). But in means of scores of Phone deletion and Nonword reading tasks were not significant different between two groups (P=0.919, P=0.670).Discussion: Cochlear implant with accessibility auditory inputs can facilitated the acquisition of phonological awareness skills in hearing loss children. But whereas the other language inputs such as sight and touch input helped to developing these skills, children with hearing aids too also can acquisition these skills.
A Probabilistic Approach to Analysis of Reliability in n-D Meshes with Interconnect Router Failures
Farshad Safaei,Majed ValadBeigi
International Journal of Computer Networks & Communications , 2011,
Abstract: The routing algorithms for parallel computers, on-chip networks, multi-core processors, andmultiprocessors system-on-chip (MP-SoCs) exhibit router failures must be able to handle interconnectrouter failures that render a symmetrical mesh non-symmetrically. When developing a routingmethodology, the time complexity of calculation should be minimal, and thus complicated routingstrategies to introduce profitable paths may not be appropriate. Several reports have been released inthe literature on using the concept of fault rings to provide detour paths to messages blocked by faultsand to route messages around the fault regions. In order to analyze the performance of such algorithms,it is required to investigate the characteristics of fault rings. In this paper, we introduce a novelperformance index of network reliability presenting the probability of message facing fault rings, andevaluating the performance-related reliability of adaptive routing schemes in n-D mesh-basedinterconnection networks with a variety of common cause fault patterns. Sufficient simulation results ofMonte-Carlo method are conducted to demonstrate the correctness of the proposed analytical model.
A Probabilistic Approach to Analysis of Reliability in n-D Meshes with Interconnect Router Failures
Farshad Safaei,Majed ValadBeigi
Computer Science , 2013,
Abstract: The routing algorithms for parallel computers, on-chip networks, multi-core processors, and multiprocessors system-on-chip (MP-SoCs) exhibit router failures must be able to handle interconnect router failures that render a symmetrical mesh non-symmetrically. When developing a routing methodology, the time complexity of calculation should be minimal, and thus complicated routing strategies to introduce profitable paths may not be appropriate. Several reports have been released in the literature on using the concept of fault rings to provide detour paths to messages blocked by faults and to route messages around the fault regions. In order to analyze the performance of such algorithms, it is required to investigate the characteristics of fault rings. In this paper, we introduce a novel performance index of network reliability presenting the probability of message facing fault rings, and evaluating the performance-related reliability of adaptive routing schemes in n-D mesh-based interconnection networks with a variety of common cause fault patterns. Sufficient simulation results of Monte-Carlo method are conducted to demonstrate the correctness of the proposed analytical model.
Chaotic Properties on Time Varying Map and Its Set Valued Extension  [PDF]
Ayub Khan, Praveen Kumar
Advances in Pure Mathematics (APM) , 2013, DOI: 10.4236/apm.2013.33051
Abstract: Every autonomous dynamical system X, finduces a set-valued dynamical system \"\"on the space of compact subsets of X. In this paper we have investigated some chaotic relations between a nonautonomous dynamical system and its set valued extension.
Chaos Synchronization in Lorenz System  [PDF]
Ayub Khan, Prempal Singh
Applied Mathematics (AM) , 2015, DOI: 10.4236/am.2015.611164
Abstract: In this paper, we analyze chaotic dynamics of nonlinear systems and study chaos synchronization of Lorenz system. We extend our study by discussing other methods available in literature. We propose a theorem followed by a lemma in general and another one for a particular case of Lorenz system. Numerical simulations are given to verify the proposed theorems.
DBR: A Simple, Fast and Efficient Dynamic Network Reconfiguration Mechanism Based on Deadlock Recovery Scheme
Majed ValadBeigi,Farshad Safaei,Bahareh Pourshirazi
International Journal of VLSI Design & Communication Systems , 2012,
Abstract: Dynamic network reconfiguration is described as the process of replacing one routing function with another while the network keeps running. The main challenge is avoiding deadlock anomalies while keeping limitations on message injection and forwarding minimal. Current approaches, whose complexity is so high that their practical applicability is limited, either require the existence of extra network resources like virtual channels, or they affect the performance of the network during the reconfiguration process. In this paper we present a simple, fast and efficient mechanism for dynamic network reconfiguration which is based on regressive deadlock recoveries instead of avoiding deadlocks. The mechanism which is referred to as DBR guarantees a deadlock-free reconfiguration based on wormhole switching (WS) and it does not require additional resources. In this approach, the need for a reliable message transmission has led to a modified WS mechanism which includes additional flits or control signals. DBR allows cycles to be formed and in such conditions when a deadlock occurs, the messages suffer from time-out. Then, this method releases the buffers and channels from the current node and thus the source retransmits the message after a random time gap. Evaluating results reveal that the mechanism shows substantial performance improvements over the other methods and it works efficiently in different topologies with various routing algorithms.
DBR: A Simple, Fast and Efficient Dynamic Network Reconfiguration Mechanism Based on Deadlock Recovery Scheme
Majed ValadBeigi,Farshad Safaei,Bahareh Pourshirazi
Computer Science , 2012, DOI: 10.5121/vlsic.2012.3502
Abstract: Dynamic network reconfiguration is described as the process of replacing one routing function with another while the network keeps running. The main challenge is avoiding deadlock anomalies while keeping limitations on message injection and forwarding minimal. Current approaches, whose complexity is so high that their practical applicability is limited, either require the existence of extra network resources like virtual channels, or they affect the performance of the network during the reconfiguration process. In this paper we present a simple, fast and efficient mechanism for dynamic network reconfiguration which is based on regressive deadlock recoveries instead of avoiding deadlocks. The mechanism which is referred to as DBR guarantees a deadlock-free reconfiguration based on wormhole switching (WS) and it does not require additional resources. In this approach, the need for a reliable message transmission has led to a modified WS mechanism which includes additional flits or control signals. DBR allows cycles to be formed and in such conditions when a deadlock occurs, the messages suffer from time-out. Then, this method releases the buffers and channels from the current node and thus the source retransmits the message after a random time gap. Evaluating results reveal that the mechanism shows substantial performance improvements over the other methods and it works efficiently in different topologies with various routing algorithms.
Study on Test Compaction in High-Level Automatic Test Pattern Generation (ATPG) Platform  [PDF]
Ayub Chin Abdullah, Chia Yee Ooi
Circuits and Systems (CS) , 2013, DOI: 10.4236/cs.2013.44046
Abstract:

Advancements in semiconductor technology are making gate-level test generation more challenging. This is because a large amount of detailed structural information must be processed in the search process of automatic test pattern generation (ATPG). In addition, ATPG needs to deal with new defects caused by process variation when IC is shrinking. To reduce the computation effort of ATPG, test generation could be started earlier at higher abstraction level, which is in line with top-down design methodology that has become more popular nowadays. In this research, we employ Chen’s high-level fault model in the high-level ATPG. Besides shorter ATPG time as shown in many previous works, our study showed that high-level ATPG also contributes to test compaction. This is because most of the high-level faults correlate with the gate-level collapsed faults especially at input/output of the modules in a circuit. The high-level ATPG prototype used in our work is mainly composed by constraint-driven test generation engine and fault simulation engine. Experimental result showed that more reduced/compact test set can be generated from the high-level ATPG.

Comparison the Duration Patterns Sequence Test (DPST) Between Multiple Sclerosis and Normal Participants
A Valadbeigi,N Rouhbakhsh,G Mohamadkhani,S Jalaei
Modern Rehabilitation , 2012,
Abstract: Background and Aim: Many of multiple sclerosis (MS) patients with normal pure tone thresholds complain from difficulties in their hearing, especially perception of speech in background noise. Many tests for evaluation of this dysfunction have been developed; one of the best tests that are applied for evaluating the ability of individual to process and categorize brief, rapid changes in auditory stimuli is duration pattern sequence test (DPST). Accordingly, the purpose of this study was to compare between MS and normal 18-40-years-old participants by the duration pattern sequence test (DPST).Materials and Methods: This analytic-descriptive non-invasive cohort study was conducted on 20 relapsing-remitting MS and 26 normal subjects 18-40-year-old with normal hearing. The finding data, percent of corrected answers, in two groups was evaluated by T-test. Results: The finding showed reduction of corrected answers percentage in DPST test between two groups (P<0.05). in addition, long periods of the disease showed poor performance in DPST test in both ear. Conclusion: The findings of this study confirm that temporal resolution deficits in patient with MS may be related to involvement of central auditory processing nervous system.Keywords: Temporal Processing, Temporal Ordering, Duration Pattern Sequence Test (DPST), Multiple Sclerosis (MS)
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