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Digital Architectures for UWB Beamforming Using 2D IIR Spatio-Temporal Frequency-Planar Filters
Soumya Kondapalli,Arjuna Madanayake,Len Bruton
International Journal of Antennas and Propagation , 2012, DOI: 10.1155/2012/234263
Abstract: A design method and an FPGA-based prototype implementation of massively parallel systolic-array VLSI architectures for 2nd-order and 3rd-order frequency-planar beam plane-wave filters are proposed. Frequency-planar beamforming enables highly-directional UWB RF beams at low computational complexity compared to digital phased-array feed techniques. The array factors of the proposed realizations are simulated and both high-directional selectivity and UWB performance are demonstrated. The proposed architectures operate using 2's complement finite precision digital arithmetic. The real-time throughput is maximized using look-ahead optimization applied locally to each processor in the proposed massively-parallel realization of the filter. From sensitivity theory, it is shown that 15 and 19-bit precision for filter coefficients results in better than 3% error for 2nd- and 3rd-order beam filters. Folding together with Ktimes multiplexing is applied to the proposed beam architectures such that throughput can be traded for K-fold lower complexity for realizing the 2-D fan filter banks. Prototype FPGA circuit implementations of these filters are proposed using a Virtex 6 xc6vsx475t-2ff1759 device. The FPGA-prototyped architectures are evaluated using area (A), critical path delay (T), and metrics AT and AT 2. The L2 error energy is used as a metric for evaluating fixed-point noise levels and the accuracy of the finite precision digital arithmetic circuits. 1. Introduction Radio-frequency (RF) two-dimensional (2D) infinite impulse response (IIR) space-time (ST) plane-wave frequency-planar beam filters [1] have potential applications in ultra-wideband (UWB) directional filtering of propagating electromagnetic far-field plane-waves. Such plane-wave filters achieve highly directional beamforming for aperture array applications. The proposed beam filters are designed using the concept of frequency-planar resonant 2D inductor-capacitor (LC) ladder network prototypes having resistive terminations [2]. For example, UWB beam filters can be employed in radar [3], wireless communications [4], radio astronomy [5], and electromagnetic imaging, and sensing [6]. Furthermore, new applications have been proposed in cognitive radio towards enhanced access to radio spectrum (EARS) [7] which requires sensitive spectrum sensing in both space and time domains [8], in turn leading to a strong need for low-complexity directional filters capable of real-time RF operation [9]. High attenuation in the stop-band region as well as a sharp transition from filter passband to stop-band is
Asynchronous Realization of Algebraic Integer-Based 2D DCT Using Achronix Speedster SPD60 FPGA
Nilanka Rajapaksha,Amila Edirisuriya,Arjuna Madanayake,Renato J. Cintra
Journal of Electrical and Computer Engineering , 2013, DOI: 10.1155/2013/834793
VLSI Architecture for 8-Point AI-based Arai DCT having Low Area-Time Complexity and Power at Improved Accuracy
Amila Edirisuriya,Arjuna Madanayake,Vassil S. Dimitrov,Renato J. Cintra,Jithra Adikari
Journal of Low Power Electronics and Applications , 2012, DOI: 10.3390/jlpea2020127
Abstract: A low complexity digital VLSI architecture for the computation of an algebraic integer (AI) based 8-point Arai DCT algorithm is proposed. AI encoding schemes for exact representation of the Arai DCT transform based on a particularly sparse 2-D AI representation is reviewed, leading to the proposed novel architecture based on a new final reconstruction step (FRS) having lower complexity and higher accuracy compared to the state-of-the-art. This FRS is based on an optimization derived from expansion factors that leads to small integer constant-coefficient multiplications, which are realized with common sub-expression elimination (CSE) and Booth encoding. The reference circuit [1] as well as the proposed architectures for two expansion factors α? = 4.5958 and α′ = 167.2309 are implemented. The proposed circuits show 150% and 300% improvements in the number of DCT coefficients having error ≤ 0:1% compared to [1]. The three designs were realized using both 40 nm CMOS Xilinx Virtex-6 FPGAs and synthesized using 65 nm CMOS general purpose standard cells from TSMC. Post synthesis timing analysis of 65 nm CMOS realizations at 900 mV for all three designs of the 8-point DCT core for 8-bit inputs show potential real-time operation at 2.083 GHz clock frequency leading to a combined throughput of 2.083 billion 8-point Arai DCTs per second. The expansion-factor designs show a 43% reduction in area (A) and 29% reduction in dynamic power (PD) for FPGA realizations. An 11% reduction in area is observed for the ASIC design for α? = 4.5958 for an 8% reduction in total power ( PT ). Our second ASIC design having α′ = 167.2309 shows marginal improvements in area and power compared to our reference design but at significantly better accuracy.
Asynchronous Realization of Algebraic Integer-Based 2D DCT Using Achronix Speedster SPD60 FPGA
Nilanka Rajapaksha,Amila Edirisuriya,Arjuna Madanayake,Renato J. Cintra,Dennis Onen,Ihab Amer,Vassil S. Dimitrov
Journal of Electrical and Computer Engineering , 2013, DOI: 10.1155/2013/834793
Abstract: Transformation and quantization play a critical role in video codecs. Recently proposed algebraic-integer-(AI-) based discrete cosine transform (DCT) algorithms are analyzed in the presence of quantization, using the High Efficiency Video Coding (HEVC) standard. AI DCT is implemented and tested on asynchronous quasi delay-insensitive logic, using Achronix SPD60 field programmable gate array (FPGA), which leads to lower complexity, higher speed of operation, and insensitivity to process-voltage-temperature variations. Performance of AI DCT with HEVC is measured in terms of the accuracy of the transform coefficients and the overall rate-distortion (R-D) characteristics, using HM 7.1 reference software. Results indicate a 31% improvement over the integer DCT in the number of transform coefficients having error within 1%. The performance of the 65?nm asynchronous hardware in terms of speed of operation is investigated and compared with the 65?nm synchronous Xilinx FPGA. Considering word lengths of 5 and 6 bits, a speed increase of 230% and 199% is observed, respectively. These results indicate that AI DCT can be potentially utilized in HEVC for applications demanding high accuracy as well as high throughput. However, novel quantization schemes are required to allow the accuracy improvements obtained. 1. Introduction High dynamic range (HDR) video and image transmission over digital communication channels is undergoing exponential growth [1]. With the increasing demand for high-definition programming, there exists a strong need for efficient digital video coding (DVC) that provides high data compression ratios which in turn leads to better utilization of network resources [2]. The H.264/AVC standard [3] does not provide the required compression ratios for emerging capture and display technologies such as ultra high definition (UHD) [4], multiview [5], and autostereoscopy [6]. To address such emerging needs, the Joint Collaborative Team on Video Coding (JCT-VC) has developed the successor for H.264/AVC, called High Efficiency Video Coding (HEVC) [4]. The HEVC standard aims at achieving a 50% reduction in data rate compared with its predecessors while maintaining low complexity computation. Video compression systems operating at high frequencies and resolutions require hardware capable of significant throughput with tolerable area and power requirements. Real-time video compression circuits having high numerical accuracy are needed for next-generation video [1], coding systems [2, 3, 7], and retina displays [8]. The two-dimensional (2D) 8 8 discrete cosine
TCP-R with EPDN: Handling out of Order Packets in Error Prone Satellite Networks  [PDF]
Int'l J. of Communications, Network and System Sciences (IJCNS) , 2009, DOI: 10.4236/ijcns.2009.27078
Abstract: Studies have shown that packet reordering is common, especially in satellite networks where there are link level retransmissions and multipath routing. Moreover, traditional satellite networks exhibit high corruption rates causing packet losses. Reordering and corruption of packets decrease the TCP performance of a network, mainly because it leads to overestimation of the congestion in the network. We consider satellite networks and analyze the performance of such networks when reordering and corruption of packets occurs. We propose a solution that could significantly improve the performance of the network when reordering and corruption of packets occur in a satellite network. We report results of our simulation experiments, which support this claim.
Renaming the NCDs
Aluwihare Arjuna
Bulletin of the World Health Organization , 2002,
Analysing TCP for Bursty Traffic  [PDF]
Israfil Biswas, Arjuna Sathiaseelan, Raffaello Secchi, Gorry Fairhurst
Int'l J. of Communications, Network and System Sciences (IJCNS) , 2010, DOI: 10.4236/ijcns.2010.37078
Abstract: The Transmission Control Protocol has been designed to support interactive and bulk applications, with performance tuned to support bulk applications that desire to continuously send data. In contrast, this paper analyses TCP performance for a class of applications that do not wish to send continuous data, but instead generate bursts of data separated by application-limited periods in which little or no data is sent. In this context, the paper evaluates an experimental method, Congestion Window Validation (CWV), proposed to mitigate the network impact of bursty TCP applications. Simulation results show that TCP-CWV exhibits a conservative behaviour during application-limited periods. The results also show that TCP-CWV is able to use the available capacity after an idle period over a shared path and that this can have benefit, especially over long delay paths, when compared to slow-start restart specified by standard TCP. The paper recommends the development of CWV-like algorithms to improve the performance for bursty applications while also providing an incentive for application designers to use congestion control.
The Role of Location Based Technologies in Intelligent Transportation Systems
Nagendra R. Velaga,Arjuna Sathiaseelan
Asian Journal of Information Technology , 2012, DOI: 10.3923/ajit.2011.227.233
Abstract: Information Technology (IT) has played a significant role in enhancing the efficiency of modern day transportation systems. Recent advances in sensors, communication and information systems have enabled transportation systems to be more intelligent. Various location technologies and data integration methods (also known as map-matching algorithms) are used to support the navigation modules of such transport systems. This study provides a survey of location based technologies that encompass an Intelligent Transportation System (ITS) and provides an insight into the Required Navigation Performance (RNP) parameters that are required for decision-making in efficient delivery of transport systems. The reseachers also describe how various location sensors and map-matching algorithms are capable of supporting the navigation modules of ITS.
Constructing a Distributed AUV Network for Underwater Plume-Tracking Operations
Stephanie Petillo,Henrik Schmidt,Arjuna Balasuriya
International Journal of Distributed Sensor Networks , 2012, DOI: 10.1155/2012/191235
Abstract: In recent years, there has been significant concern about the impacts of offshore oil spill plumes and harmful algal blooms on the coastal ocean environment and biology, as well as on the human populations adjacent to these coastal regions. Thus, it has become increasingly important to determine the 3D extent of these ocean features (“plumes”) and how they evolve over time. The ocean environment is largely inaccessible to sensing directly by humans, motivating the need for robots to intelligently sense the ocean for us. In this paper, we propose the use of an autonomous underwater vehicle (AUV) network to track and predict plume shape and motion, discussing solutions to the challenges of spatiotemporal data aliasing (coverage versus resolution), underwater communication, AUV autonomy, data fusion, and coordination of multiple AUVs. A plume simulation is also developed here as the first step toward implementing behaviors for autonomous, adaptive plume tracking with AUVs, modeling a plume as a sum of Fourier orders and examining the resulting errors. This is then extended to include plume forecasting based on time variations, and future improvements and implementation are discussed.
Autonomous Vehicles Navigation with Visual Target Tracking: Technical Approaches
Zhen Jia,Arjuna Balasuriya,Subhash Challa
Algorithms , 2008, DOI: 10.3390/a1020153
Abstract: This paper surveys the developments of last 10 years in the area of vision based target tracking for autonomous vehicles navigation. First, the motivations and applications of using vision based target tracking for autonomous vehicles navigation are presented in the introduction section. It can be concluded that it is very necessary to develop robust visual target tracking based navigation algorithms for the broad applications of autonomous vehicles. Then this paper reviews the recent techniques in three different categories: vision based target tracking for the applications of land, underwater and aerial vehicles navigation. Next, the increasing trends of using data fusion for visual target tracking based autonomous vehicles navigation are discussed. Through data fusion the tracking performance is improved and becomes more robust. Based on the review, the remaining research challenges are summarized and future research directions are investigated.
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